US4757523A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed testing of integrated circuit
Assignee: Texas Instruments Inc
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Filing: 1986-12-29
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Granted: 1988-07-12
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Expires: 2006-12-29
Abstract
Abstract A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.
Inventors
- 👤 Bao G. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:51
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318522; G01R31/318527; G11; G11C; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
101 words
A counter circuit having a test mode of operation, comprising: a plurality of binary counter stages, each stage having an input and an output, decoder means having an input receiving all of said outputs from the counter stages and coupling means applying selected signals to said inputs of the counter stages, means to add a binary 1 to the least significant bit of the counter stages, logic gate means receiving all of said outputs of the counter stages to produce a single output in a test mode, said coupling means including means for inverting said selected signals in said test mode.
Claim 2
Dependent Claim
101 words
A counter circuit having a test mode of operation, comprising: a plurality of binary counter stages, each stage having an input and an output, decoder means having an input receiving all of said outputs from the counter stages and coupling means applying selected signals to said inputs of the counter stages, means to add a binary 1 to the least significant bit of the counter stages, logic gate means receiving all of said outputs of the counter stages to produce a single output in a test mode, said coupling means including means for inverting said selected signals in said test mode.
Claim 3
Dependent Claim
15 words
A circuit according to claim 1 wherein said logic gate means includes an AND gate.
Claim 4
Dependent Claim
15 words
A circuit according to claim 1 wherein said logic gate means includes an OR gate.
Claim 5
Dependent Claim
19 words
A circuit according to claim 1 wherein said logic gate means includes an AND gate and an OR gate.
Claim 6
Dependent Claim
21 words
A circuit according to claim 4 including means for activating said AND gate and said OR gate in successive operating cycles.
Claim 7
Dependent Claim
26 words
A circuit according to claim 5 including means for activating said means for inverting on one of said successive operating cycles but not in the other.
Claim 8
Independent Claim
129 words
A method of testing a multiple-bit counter register in a semiconductor memory device or the like comprising the steps of: loading a fixed value into said register, said fixed value selected from a set of fixed values including all 1's and all 0's, detecting the contents of said register in logic means and producing an indication at a single terminal of said device of the presence of said fixed value in said register, said indication having significantly fewer bits than said register, altering the contents of said register according to a selected function of said fixed value, again detecting the contets of said register in said logic means and producing an indication at said terminal of said device of the presence of said selected function of the fixed value.
Claim 9
Independent Claim
129 words
A method of testing a multiple-bit counter register in a semiconductor memory device or the like comprising the steps of: loading a fixed value into said register, said fixed value selected from a set of fixed values including all 1's and all 0's, detecting the contents of said register in logic means and producing an indication at a single terminal of said device of the presence of said fixed value in said register, said indication having significantly fewer bits than said register, altering the contents of said register according to a selected function of said fixed value, again detecting the contets of said register in said logic means and producing an indication at said terminal of said device of the presence of said selected function of the fixed value.
Claim 10
Dependent Claim
28 words
A method according to claim 7 including the steps of: again altering the contents of said register according to another selected function of the contents of said register.
Claim 11
Dependent Claim
24 words
A method according to claim 8 including the step of again detecting the contents of said register and producing said indication at said terminal.
Claim 12
Dependent Claim
13 words
A method according to claim 7 wherein said fixed value is all 1's.
Claim 13
Dependent Claim
24 words
A method according to claim 10 wherein said first step of detecting employs determining an AND logic function of the contents of the register.
Claim 14
Dependent Claim
24 words
A method according to claim 11 wherein said second step of detecting employs determining an OR logic function of the contents of the register.
Claim 15
Dependent Claim
41 words
A method according to claim 7 wherein said step of altering includes toggling the LSB of the register and transposing the carry between bits of the register to produce a condition where all bits of the register should be the same.
Claim 16
Dependent Claim
13 words
A method according to claim 13 wherein said device is an integrated circuit.
Claim 17
Dependent Claim
13 words
A method according to claim 7 wherein said device is an integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |