Three-dimensional memory card structure with internal direct chip attachment

Claim 1

A process for producing a card structure having an internal three dimensional array of semiconductor chips, comprising: providing a thermal conductor plane; applying a first compliant dielectric material on major surfaces of said thermal conductor plane, said first compliant dielectric material having a low dielectric constant and further having a thermal coefficient of expansion compatible with the thermal coefficient of expansion of said semiconductor chips and said thermal conductor plane, whereby thermal expansion stability with said semiconductor chips and said thermal conductor plane is maintained; forming a two dimensional array of chip wells in said dielectric material on each side of said thermal conductor plane; positioning and securing said semiconductor chips in respective ones of said chip wells; laminating a lead frame mounted on a carrier sheet over said first compliant dielectric material and said semiconductor chips; forming an electrical connection between each of said semiconductor chips and said lead frame; encapsulating said electrical connections with a filler; laminating an insulating layer and a wiring plane over said encapsulated connections; electrically connecting said lead frame and said wiring plane so as to form a chip core; and electrically connecting a power core to said chip core, said power core comprising: at least one electrical conductor plane; and a second compliant dielectric material on the major surfaces of said electrical conductor plane, said second compliant dielectric material having a thermal coefficient of expansion compatible with said electrical conductor plane, whereby thermal expansion stability with said electrical conductor plane is maintained.