Patent US5226015A successfully refreshed from Google Patents.
US5226015A
Expired / Lapsed
US
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Semiconductor memory system
Assignee: Toshiba Corp
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Filing: 1991-05-28
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Granted: 1993-07-06
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Expires: 2011-05-28
Abstract
Abstract A programmable semiconductor memory system employs an EPROM. The system holds the start and end addresses of each write operation to completely use a data storage region of the EPROM with no redundancy and with no limitation on the quantity of data to be written if the quantity is within the capacity of the EPROM.
Inventors
- 👤 Masaji Gotou
- 👤 Hidehito Usui
- 👤 Hitoshi Kondo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:17
CPC Classifications
G; G11; G11C; G11C29/00; G11C16/00; G11C16/02; G11C16/06; G11C16/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
154 words
A semiconductor memory system comprising: a data storage region of an EPROM; a write controller for writing data into a part of said data storage region; a number storage region of the EPROM, for storing the number of write operations done by said write controller; an address storage region of the EPROM, for separately storing a write start address and a write end address of said data storage region for each write operation; and a bank switching controller for holding, as an address, a write start address stored in said address storage region and corresponding to the number stored in said number storage region, at a start of reading data out of said data storage region, and holding, as an address, an address next to a write end address stored in said address storage region and corresponding to the number stored in said number storage region, in writing data into said data storage region.
Claim 2
Dependent Claim
154 words
A semiconductor memory system comprising: a data storage region of an EPROM; a write controller for writing data into a part of said data storage region; a number storage region of the EPROM, for storing the number of write operations done by said write controller; an address storage region of the EPROM, for separately storing a write start address and a write end address of said data storage region for each write operation; and a bank switching controller for holding, as an address, a write start address stored in said address storage region and corresponding to the number stored in said number storage region, at a start of reading data out of said data storage region, and holding, as an address, an address next to a write end address stored in said address storage region and corresponding to the number stored in said number storage region, in writing data into said data storage region.
Claim 3
Dependent Claim
35 words
The semiconductor storage system according to claim 1, wherein said data storage region, said number storage region and address storage region, said write controller, and said bank switching controller are formed on separate chips, respectively.
Claim 4
Dependent Claim
35 words
The semiconductor memory system according to claim 1, wherein said number storage region and address storage region are formed on a chip which is different from a chip where said data storage region is formed.
Claim 5
Dependent Claim
33 words
The semiconductor memory system according to claim 1, wherein said data storage region, number storage region, address storage region, write controler, and bank switching controller are integrally formed on a single semiconductor chip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |