Patent US5222223A successfully refreshed from Google Patents.
US5222223A
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Method and apparatus for ordering and queueing multiple memory requests
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-02-03
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Granted: 1993-06-22
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Expires: 2009-02-03
Abstract
Abstract In a pipelined computer system, memory access functions are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical addresses resulting from the translation buffer 30 are passed to a cache 28 of the main memory 14 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.
Inventors
- 👤 David A. Webb, Jr.
- 👤 Ricky C. Hetherington
- 👤 John E. Murray
- 👤 Tryggve Fossum
- 👤 Dwight P. Manley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
218 words
An apparatus for controlling independent memory access requests originating from a plurality of pipelined stages in a pipelined computer system, comprising: first multiplexing means for selecting a selected one of said memory access requests from a selected one of said pipelined stages in said pipelined computer system according to a first priority scheme; a translation buffer for receiving said selected one of said memory access requests from said first multiplexing means, and converting said selected one of said memory access requests to a physical memory address; a plurality of storage locations for temporarily storing physical memory addresses from said translation buffer; second multiplexing means for selecting a selected physical address from among stored physical addresses from said storage locations according to a second priority scheme, said second priority scheme being based upon the pipelined stages in said pipelined computer system from which memory access requests corresponding to said stored physical addresses originated; and a cache memory for receiving said selected one physical address from said second multiplexing means, comparing said selected physical address to addresses currently maintained in said cache memory, accessing data stored in said cache memory at said selected physical address in response to a hit, and initiating a transfer of data from a main memory to said cache memory in response to detecting a miss.
Claim 2
Independent Claim
218 words
An apparatus for controlling independent memory access requests originating from a plurality of pipelined stages in a pipelined computer system, comprising: first multiplexing means for selecting a selected one of said memory access requests from a selected one of said pipelined stages in said pipelined computer system according to a first priority scheme; a translation buffer for receiving said selected one of said memory access requests from said first multiplexing means, and converting said selected one of said memory access requests to a physical memory address; a plurality of storage locations for temporarily storing physical memory addresses from said translation buffer; second multiplexing means for selecting a selected physical address from among stored physical addresses from said storage locations according to a second priority scheme, said second priority scheme being based upon the pipelined stages in said pipelined computer system from which memory access requests corresponding to said stored physical addresses originated; and a cache memory for receiving said selected one physical address from said second multiplexing means, comparing said selected physical address to addresses currently maintained in said cache memory, accessing data stored in said cache memory at said selected physical address in response to a hit, and initiating a transfer of data from a main memory to said cache memory in response to detecting a miss.
Claim 3
Dependent Claim
60 words
An apparatus, as set forth in claim 1, wherein said second multiplexing means includes a multiplexer, said multiplexer has an input connected to said translation buffer for receiving said physical memory addresses from said translation buffer, and said multiplexer has an output connected to an input of said cache memory for transmitting said physical memory addresses to said cache memory.
Claim 4
Independent Claim
182 words
A method of controlling independent memory access requests originating from a plurality of pipelined stages in a pipelined computer system, comprising the steps of: selecting a selected one of said memory access requests from a selected one of said pipelined stages in said pipelined computer system according to a first priority scheme; converting said selected one of said memory access requests to a physical memory address; temporarily storing, in a plurality of storage locations, physical addresses converted from corresponding ones of said memory access requests; selecting a selected physical address from among stored physical addresses from said storage locations according to a second priority scheme, said second priority scheme being based upon the pipelined stages in said pipelined computer system from which memory access requests corresponding to said stored physical addresses originated; and comparing said selected physical address to addresses currently maintained in a cache memory, accessing data stored in said cache memory at said selected address in response to a hit, and initiating a transfer of data from a main memory to said cache memory in response to detecting a miss.
Claim 5
Independent Claim
182 words
A method of controlling independent memory access requests originating from a plurality of pipelined stages in a pipelined computer system, comprising the steps of: selecting a selected one of said memory access requests from a selected one of said pipelined stages in said pipelined computer system according to a first priority scheme; converting said selected one of said memory access requests to a physical memory address; temporarily storing, in a plurality of storage locations, physical addresses converted from corresponding ones of said memory access requests; selecting a selected physical address from among stored physical addresses from said storage locations according to a second priority scheme, said second priority scheme being based upon the pipelined stages in said pipelined computer system from which memory access requests corresponding to said stored physical addresses originated; and comparing said selected physical address to addresses currently maintained in a cache memory, accessing data stored in said cache memory at said selected address in response to a hit, and initiating a transfer of data from a main memory to said cache memory in response to detecting a miss.
Claim 6
Dependent Claim
47 words
A method, as set forth in claim 3, further including the steps of temporarily ignoring a missed physical address in response to detecting a miss in said cache memory, and delivering a next highest priority physical address from one of said storage locations to said cache memory.
Claim 7
Dependent Claim
35 words
A method, as set forth in claim 4, further including the step of delivering said missed physical address to said cache memory in response to said cache memory receiving data transferred from said main memory.
Claim 8
Independent Claim
245 words
A method of servicing memory access requests originating from an instruction decoder, an operand processing unit, and an execution unit in a pipelined computer system, said method comprising the steps of: (a) selecting said memory access requests according to a first priority scheme in which requests from the execution unit have priority over requests from the operand processing unit and from the instruction decoder, and requests from the operand processing unit have priority over requests from the instruction decoder, (b) using a translation buffer to translate virtual addresses for the memory access requests selected in step (a) to corresponding physical memory addresses, (c) temporarily storing said corresponding physical memory addresses in at least three registers, (d) selecting the physical memory addresses stored in said registers based upon their corresponding memory access requests according to a second priority scheme in which requests from the execution unit have priority over requests from the operand processing unit and from the instruction decoder, and requests from the operand processing unit have priority over requests from the instruction decoder, (e) delivering the physical memory addresses selected in step (d) to a cache memory, comparing the selected physical address to addresses currently maintained in said cache memory, accessing data stored at the selected physical address when the selected physical addresses are currently maintained in the cache memory, and transferring data from a main memory to the cache memory when the selected physical addresses are not currently maintained in the cache memory.
Claim 9
Independent Claim
245 words
A method of servicing memory access requests originating from an instruction decoder, an operand processing unit, and an execution unit in a pipelined computer system, said method comprising the steps of: (a) selecting said memory access requests according to a first priority scheme in which requests from the execution unit have priority over requests from the operand processing unit and from the instruction decoder, and requests from the operand processing unit have priority over requests from the instruction decoder, (b) using a translation buffer to translate virtual addresses for the memory access requests selected in step (a) to corresponding physical memory addresses, (c) temporarily storing said corresponding physical memory addresses in at least three registers, (d) selecting the physical memory addresses stored in said registers based upon their corresponding memory access requests according to a second priority scheme in which requests from the execution unit have priority over requests from the operand processing unit and from the instruction decoder, and requests from the operand processing unit have priority over requests from the instruction decoder, (e) delivering the physical memory addresses selected in step (d) to a cache memory, comparing the selected physical address to addresses currently maintained in said cache memory, accessing data stored at the selected physical address when the selected physical addresses are currently maintained in the cache memory, and transferring data from a main memory to the cache memory when the selected physical addresses are not currently maintained in the cache memory.
Claim 10
Dependent Claim
50 words
A method, as set forth in claim 6, wherein said step (a) includes selecting memory access requests from a translation buffer fix-up unit, and wherein said first priority scheme gives said translation buffer fix-up unit priority over requests from said instruction decoder, said operand processing unit and said instruction unit.
Claim 11
Dependent Claim
63 words
A method, as set forth in claim 4, further including the step of temporarily delaying the transfer of data from the main memory to the cache memory to select a next highest priority physical address stored in said registers and access data stored at said next highest priority physical address when the next highest priority physical address is currently maintained in said cache.
Claim 12
Dependent Claim
46 words
A method, as set forth in claim 8, wherein said step (d) includes selecting a physical address from a write queue, and wherein said second priority scheme gives said write queue priority over requests from said instruction decoder, said operand processing unit and said execution unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-21 | 1996-12-21 | 1997-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-21 | 2000-12-21 | 2001-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-21 | 2004-12-21 | 2005-06-22 | $7700.00 | Window Closed / Lapsed |