Shift register useful as a select line scanner for liquid crystal display

Claim 1

A shift register comprising a plurality of substantially identical cascaded stages, each of said stages having an input terminal and an output terminal, said shift register including means for providing a plurality of phase shifted clock signals and means for providing an input signal; each of said stages comprising: an output circuit for switching the voltage on said output terminal between high and low values, said output circuit including a first solid state device for transferring a first of said clock signals to said output terminal in response to a first switching signal, and a second solid state device for transferring a low voltage to said output terminal in response to a second switching signal, said first and second said solid state devices having conduction paths serially connected at said output terminal; a first switching circuit for receiving an input signal at said input terminal, said first switching circuit including a first node for providing said first switching signal to said first solid state device in response to said input signal; and a second switching circuit for receiving a second of said clock signals, said second switching circuit including a second node for providing said second switching signal to said second solid state device in response to said second clock signal and a third solid state device in response to said input signal for maintaining said second node at a low potential when said second clock signal initially goes high.