US3909627A
Expired / Lapsed
US
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Two-phase dynamic logic circuit
Assignee: NEC Corp
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Filing: 1973-11-06
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Granted: 1975-09-30
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Expires: 1993-11-06
Abstract
Abstract A two-phase dynamic logic circuit comprises first, second, and third MOS transistors and a logic means which includes an input terminal and an output terminal. The drain of the first transistor is connected to a D.C. voltage or to the first clock signal source and the gate of that transistor as well as the drain of the third transistor are connected to the first clock signal source. The sources of the first and second transistors are connected to the output terminal of the logic means. The gate of the second transistor is connected to the second clock signal source, and the drain of that transistor is connected to the gate of the third transistor. The output signal of the circuit is derived from the source of the third transistor.
Inventors
- 👤 Masatoshi Mizuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
227 words
A two-phase dynamic logic circuit comprising first, second and third insulated-gate field effect transistors each having a drain, source and gate, a first clock signal source generating a first pulse and a second pulse succeeding said first pulse, a second clock signal source generating a third pulse between said first and second pulses, logic means having an input terminal and an output terminal, said output terminal of said logic means being connected to the sources of said first and second insulated-gate field effect transistors, the drain of said first insulated-gate field effect transistor being connected to one of a D.C. voltage source and said first clock signal source, the gate of said first insulated-gate field effEct transistor and the drain of said thrid insulated-gate field effect transistor being connected to said first clock signal source, the gate of said second insulated-gate field effect transistor being connected to said second clock signal source, and the drain of said second insulated-gate field effect transistor being connected to the gate of said third insulated-gate field effect transistor, wherein in response to the input signal supplied to said input terminal of said logic means during the period of time when said third pulse is generated, an output signal is derived from the source of said third insulated-gate field effect transistor during the period of time when said second pulse is generated.
Claim 2
Dependent Claim
227 words
A two-phase dynamic logic circuit comprising first, second and third insulated-gate field effect transistors each having a drain, source and gate, a first clock signal source generating a first pulse and a second pulse succeeding said first pulse, a second clock signal source generating a third pulse between said first and second pulses, logic means having an input terminal and an output terminal, said output terminal of said logic means being connected to the sources of said first and second insulated-gate field effect transistors, the drain of said first insulated-gate field effect transistor being connected to one of a D.C. voltage source and said first clock signal source, the gate of said first insulated-gate field effEct transistor and the drain of said thrid insulated-gate field effect transistor being connected to said first clock signal source, the gate of said second insulated-gate field effect transistor being connected to said second clock signal source, and the drain of said second insulated-gate field effect transistor being connected to the gate of said third insulated-gate field effect transistor, wherein in response to the input signal supplied to said input terminal of said logic means during the period of time when said third pulse is generated, an output signal is derived from the source of said third insulated-gate field effect transistor during the period of time when said second pulse is generated.
Claim 3
Dependent Claim
148 words
The two-phase dynamic logic circuit according to claim 1, further comprising fourth, fifth and sixth insulated-gate field effect transistors each having a gate, source and drain, the drains of said fourth and fifth insulated-gate field effect transistors and the gate of said fourth insulated-gate field effect transistor being respectively connected to the gate of said second insulated-gate field effect transistor, the sources of said fourth and fifth insulated-gate field effect transistors being respectively connected to the gate of said sixth insulated-gate field effect transistor, the gate of said fifth insulated-gate field effect transistor being connected to the gate of said third insulated-gate field effect transistor, and the drain of said sixth insulated-gate field effect transistor being connected to the drain of said third insulated-gate field effect transistor, wherein first and second output signals are derived from the sources of said third and sixth insulated-gate field effect transistors, respectively.
Claim 4
Dependent Claim
51 words
The two-phase dynamic logic circuit according to claim 2, in which said logic means comprises a seventh insulated-gate field effect transistor having a source connected to the ground, a drain connected to the output terminal of said logic means, and a gate connected to the input terminal of said logic means.
Claim 5
Dependent Claim
199 words
The two-phase dynamic logic circuit according to claim 2, in which said logic means comprises insulated-gate field effect transistors arranged in the form of a matrix of m-rows and n-columns (wherein m and n denote integers greater than 1) and (m-1) additional insulated-gate field effect transistors; the insulated-gate field effect transistors included in each column of said matrix being connected in series respectively, the insulated-gate field effect transistors included in each row of said matrix being connected in parallel respectively, said additional insulated-gate field effect transistors being connected respectively in parallel to the insulated-gate field effect transistors included in (m-1) numbers of said rows except for a single row of said matrix, the gates of said additional insulated-gate field effect transistors being connected to said first clock signal source, the gates of the insulated-gate field effect transistors arranged in said matrix being connected to said input terminals of said logic means respectively, the drains of the insulated-gate field effect transistors included in the first row of said matrix being connected to said output terminal of said logic means, and the sources of the insulated-gate field effect transistors included in said single row of said matrix being connected to ground.
Claim 6
Dependent Claim
46 words
The two-phase dynamic logic circuit according to claim 1, further comprising a first capacitor element connected between the gate and source of said second insulated-gate field effect transistor, and a second capacitor element connected between the gate and source of said third insulated-gate field effect transistor.
Claim 7
Dependent Claim
76 words
The two-phase logic circuit according to claim 1, further comprising a fourth insulated-gate field effect transistor having a gate, drain and source, the gate of said fourth insulated-gate field effect transistor being connected to the gate of said second insulated-gate field effect transistor, tHe drain of said fourth insulated-gate field effect transistor being connected to the source of said third insulated-gate field effect transistor, and the source of said fourth insulated-gate field effect transistor being grounded.
Claim 8
Dependent Claim
51 words
The two-phase dynamic logic circuit according to claim 1, in which said logic means comprises a fourth insulated-gate field effect transistor having a source connected to the ground, a drain connected to the output terminal of said logic means, and a gate connected to the input terminal of said logic means.
Claim 9
Dependent Claim
199 words
The two-phase dynamic logic circuit according to claim 1, in which said logic means comprises insulated-gate field effect transistors arranged in the form of a matrix of m-rows and n-columns (wherein m and n denote integers greater than 1) and (m-1) additional insulated-gate field effect transistors, the insulated-gate field effect transistors included in each column of said matrix being connected in series respectively, the insulated-gate field effect transistors included in each row of said matrix being connected in parallel respectively, said additional insulated-gate field effect transistors being connected respectively in parallel to the insulated-gate field effect transistors included in (m-1) numbers of said rows except for a single row of said matrix, the gates of said additional insulated-gate field effect transistors being connected to said first clock signal source, the gates of the insulated-gate field effect transistors arranged in said matrix being connected to said input terminals of said logic means respectively, the drains of the insulated-gate field effect transistors included in the first row of said matrix being connected to said output terminal of said logic means, and the sources of the insulated-gate field effect transistors included in said single row of said matrix being connected to ground.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |