US3937984A
Expired / Lapsed
US
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Shift registers
Assignee: Integrated Photomatrix Ltd
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Filing: 1974-10-07
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Granted: 1976-02-10
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Expires: 1994-10-07
Abstract
Abstract A shift register stage comprises an MOS gating transistor having its drain and source electrodes connected respectively to an input node receiving pulses to be shifted through the stage and a gate electrode of an MOS amplifying transistor. A capacitor is connected between the gate and source electrodes of the amplifying transistor. The source electrode of the amplifying transistor constitutes the output of the stage and is connected to the drain electrode of a current source transistor having its source electrode connected to an earth line and its gate electrode connected to a reference potential. The gate electrode of the gating transistor is connected to receive a first series of clock pulses, and the drain electrode of the amplifying transistor is connected to receive another series of clock pulses in non-overlapping relation with the first series.
Inventors
- 👤 Peter William Fry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:06
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/186
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
A shift register stage comprising: an input node for receiving pulses to be shifted through the stage; a single amplifying element having a non-inverting signal input electrode, a current input electrode and an output electrode which constitutes the output of the stage; an input gate means which is connected between the input node and the signal input electrode of the amplifying element, said input gate means having a control electrode; charge storage means connected between the signal input electrode and the output electrode of the amplifying element; and a current source connected between the output electrode of the amplifying element and a clock pulse reference potential, said current source having a control electrode connected to a second reference potential continuously biasing the current source for conduction; said control electrode of said input gate means being connected to receive one series of clock pulses; said current input electrode of said amplifying element being connected to receive another series of clock pulses in non-overlapping relation with the pulses of the first series.
Claim 2
Dependent Claim
170 words
A shift register stage comprising: an input node for receiving pulses to be shifted through the stage; a single amplifying element having a non-inverting signal input electrode, a current input electrode and an output electrode which constitutes the output of the stage; an input gate means which is connected between the input node and the signal input electrode of the amplifying element, said input gate means having a control electrode; charge storage means connected between the signal input electrode and the output electrode of the amplifying element; and a current source connected between the output electrode of the amplifying element and a clock pulse reference potential, said current source having a control electrode connected to a second reference potential continuously biasing the current source for conduction; said control electrode of said input gate means being connected to receive one series of clock pulses; said current input electrode of said amplifying element being connected to receive another series of clock pulses in non-overlapping relation with the pulses of the first series.
Claim 3
Dependent Claim
49 words
A shift register stage as claimed in claim 1, wherein the amplifying element comprises a metal-oxide semiconductor field-effect amplifying transistor having a gate electrode which constitutes the non-inverting signal input electrode and current-carrying electrodes which respectively constitute the output electrode and the current input electrode of the amplifying element.
Claim 4
Dependent Claim
53 words
A shift register stage as claimed in claim 1, wherein the input gate means comprises a metal-oxide semiconductor field-effect gating transistor having current-carrying electrodes connected respectively to the input node and the signal input electrode of the amplifying element and a gate electrode connected to receive the said one series of clock pulses.
Claim 5
Dependent Claim
31 words
A shift register stage as claimed in claim 1, wherein the charge storage means comprises a capacitor connected between the signal input electrode and the output electrode of the amplifying element.
Claim 6
Dependent Claim
59 words
A shift register stage as claimed in claim 1, wherein the current source comprises a metal-oxide semiconductor field-effect current source transistor having current-carrying electrodes connected respectively to the output of the amplifying element and the clock pulse reference potential and a gate electrode connected to receive said second reference potential adapted to bias the current source transistor for conduction.
Claim 7
Dependent Claim
264 words
A shift register circuit comprising: a plurality of stages, each stage including an input node for receiving pulses to be shifted through the stage; a single amplifying element having a non-inverting signal input electrode, a current input electrode and an output electrode which constitutes the output of the stage; an input gate means which is connected between the input node and the signal input electrode of the amplifying element, said input gate means having a control electrode; charge storage means connected between the signal input electrode and the output electrode of the amplifying element; and a current source connected between the output electrode of the amplifying element and a clock pulse reference potential, said current source having a control electrode connected to a second reference potential continuously biasing the current source for conduction; means connecting the output electrode of at least selected of said stages to the respective input node of the next succeeding stage in the shift register circuit, the said control electrode of a said input gate means for a given stage being connected to receive a first series of clock pulses, and said current input electrode of said amplifying element of the same given stage being connected to receive a second series of clock pulses in non-overlapping relation with the pulses of the first series, and wherein a next succeeding stage following said given stage has the control electrode of its input gate means connected to receive the second series of clock pulses, and the current input electrode of its amplifying element connected to receive said first series of clock pulses.
Claim 8
Dependent Claim
264 words
A shift register circuit comprising: a plurality of stages, each stage including an input node for receiving pulses to be shifted through the stage; a single amplifying element having a non-inverting signal input electrode, a current input electrode and an output electrode which constitutes the output of the stage; an input gate means which is connected between the input node and the signal input electrode of the amplifying element, said input gate means having a control electrode; charge storage means connected between the signal input electrode and the output electrode of the amplifying element; and a current source connected between the output electrode of the amplifying element and a clock pulse reference potential, said current source having a control electrode connected to a second reference potential continuously biasing the current source for conduction; means connecting the output electrode of at least selected of said stages to the respective input node of the next succeeding stage in the shift register circuit, the said control electrode of a said input gate means for a given stage being connected to receive a first series of clock pulses, and said current input electrode of said amplifying element of the same given stage being connected to receive a second series of clock pulses in non-overlapping relation with the pulses of the first series, and wherein a next succeeding stage following said given stage has the control electrode of its input gate means connected to receive the second series of clock pulses, and the current input electrode of its amplifying element connected to receive said first series of clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-09 | 1979-08-11 | 1980-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-09 | 1983-08-11 | 1984-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-09 | 1987-08-11 | 1988-02-10 | $7700.00 | Window Closed / Lapsed |