US4890308A
Expired / Lapsed
US
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Scanning pulse generating circuit
Assignee: Olympus Corp
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Filing: 1988-09-06
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Granted: 1989-12-26
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Expires: 2008-09-06
Abstract
Abstract A scanning pulse generating circuit has a multiplicity of stages constitued by first basic circuits and second basic circuits which are connected to appear alternatingly in a cascade manner. The first basic circuit is composed of three or four MOS transistors and a feedback capacitor, and includes at least a bootstrap inverter, so as to produce predetermined output pulses upon receipt of driving synchronizing pulses. The second basic circuit has the same construction as the first basic circuit except that it receives different driving synchronizing pulse from that used in the first basic circuit. The output pulses from the respective basic circuits are free from drop of voltage and fluctuation, by virtue of the bootstrap effect. In addiition, power consumption can be reduced without difficulty.
Inventors
- 👤 Masaharu Imai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:49
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
319 words
A scanning pulse generating circuit comprising: (a) a plurality of first basic circuits each including: a first MOS transistor with the gate terminal thereof serving as an input terminal; a second MOS transistor connected in series to said first MOS transistor with one of main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a first synchronizing pulse; a third MOS transistor having the gate terminal therof connected to the point of juncture between said first and second MOS transistors while one of the main electrodes thereof being connected to a power supply; a fourth MOS transistor connected in series to said third MOS transistor with one of the main electrodes thereof being grounded while the gate electrode thereof being capable of receiving a second synchronizing pulse; and a first capacitive element connected between the point of juncture between said first and second MOS transistors and the point of juncture between said third and fourth MOS transistors, the point of juncture between said third and fourth MOS transistors constituting an output terminal; and (b) a plurality of second basic circuits each including: fifth, sixth, seventh and eighth MOS transistors corresponding to said first, second, third and fourth MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element; said fifth, sixth, seventh and eighth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements in said first basic circuit, said output terminal of said first basic circuit being connected to the gate terminal of said fifth MOS transistor, the gate terminals of said sixth and eighth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternately in a multiplicity of stages so that scanning pulses are derived from the output terminals of said basic circuits of the successive stages.
Claim 2
Dependent Claim
319 words
A scanning pulse generating circuit comprising: (a) a plurality of first basic circuits each including: a first MOS transistor with the gate terminal thereof serving as an input terminal; a second MOS transistor connected in series to said first MOS transistor with one of main electrodes thereof being grounded while the gate terminal thereof being capable of receiving a first synchronizing pulse; a third MOS transistor having the gate terminal therof connected to the point of juncture between said first and second MOS transistors while one of the main electrodes thereof being connected to a power supply; a fourth MOS transistor connected in series to said third MOS transistor with one of the main electrodes thereof being grounded while the gate electrode thereof being capable of receiving a second synchronizing pulse; and a first capacitive element connected between the point of juncture between said first and second MOS transistors and the point of juncture between said third and fourth MOS transistors, the point of juncture between said third and fourth MOS transistors constituting an output terminal; and (b) a plurality of second basic circuits each including: fifth, sixth, seventh and eighth MOS transistors corresponding to said first, second, third and fourth MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element; said fifth, sixth, seventh and eighth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements in said first basic circuit, said output terminal of said first basic circuit being connected to the gate terminal of said fifth MOS transistor, the gate terminals of said sixth and eighth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternately in a multiplicity of stages so that scanning pulses are derived from the output terminals of said basic circuits of the successive stages.
Claim 3
Dependent Claim
52 words
A scanning pulse generating circuit as set forth in claim 1, wherein the other of said main electrodes of said first MOS transistor of said first basic circuit and the other of said main electrodes of said fifth MOS transistor of said second basic circuit are respectively connected to said power supply.
Claim 4
Dependent Claim
56 words
A scaning pulse generating circuit as set forth in claim 1, wherein the other of said main electrodes of said first MOS transistor of said first basic circuit and the other of said main electrodes of said fifth MOS transistor of said second basic circuit are connected to the gate terminals of the respective MOS transistors.
Claim 5
Dependent Claim
26 words
A scanning pulse generating circuit as set forth in claim 1, wherein each of said first and second capacitive elements are constituted by a MOS diode.
Claim 6
Dependent Claim
26 words
A scanning pulse generating circuit as set forth in claim 2, wherein each of said first and second capacitive elements are constituted by a MOS diode.
Claim 7
Dependent Claim
26 words
A scanning pulse generating circuit as set forth in claim 3, wherein each of said first and second capacitive elements are constituted by a MOS diode.
Claim 8
Dependent Claim
40 words
A scanning pulse generating circuit as set forth in claim 1, wherein only the outputs from the group of said first basic circuits or the outputs from the group of said second basic circuits are used as the scanning pulses.
Claim 9
Dependent Claim
304 words
A scanning pulse generating circuit comprising: (a) a plurality of first basic circuit each including: a first MOS transistor having an input terminal constituted by one of the main electrodes thereof while the gate terminal thereof being capable of receiving a first synchronizing pulse; a second MOS transistor with the gate terminal thereof connected to the other of the main electrodes of said first MOS transistor and with one of the main electrodes thereof connected to a power supply; a third MOS transistor connected in series to said second MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof is capable of receiving a second synchronizing pulse; and a first capacitive element connected between said gate terminal of said second MOS transistor and the point of juncture between said second and third MOS transistors, said point of juncture between said second and third MOS transistors serving as an output terminal; and (b) a plurality of second basic circuits each including: fourth, fifth and sixth MOS transistors corresponding to said first, second and third MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element of said first basic circuit; said fourth, fifth and sixth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements of said first basic circuit, said output terminal of said first basic circuit being connected to one of the main electrodes of said fourth MOS transistor, the gate terminals of said fourth and sixth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are successively output from said output terminals of said basic circuits of the successive stages.
Claim 10
Dependent Claim
304 words
A scanning pulse generating circuit comprising: (a) a plurality of first basic circuit each including: a first MOS transistor having an input terminal constituted by one of the main electrodes thereof while the gate terminal thereof being capable of receiving a first synchronizing pulse; a second MOS transistor with the gate terminal thereof connected to the other of the main electrodes of said first MOS transistor and with one of the main electrodes thereof connected to a power supply; a third MOS transistor connected in series to said second MOS transistor with one of the main electrodes thereof being grounded while the gate terminal thereof is capable of receiving a second synchronizing pulse; and a first capacitive element connected between said gate terminal of said second MOS transistor and the point of juncture between said second and third MOS transistors, said point of juncture between said second and third MOS transistors serving as an output terminal; and (b) a plurality of second basic circuits each including: fourth, fifth and sixth MOS transistors corresponding to said first, second and third MOS transistors of said first basic circuit, respectively; and a second capacitive element corresponding to said first capacitive element of said first basic circuit; said fourth, fifth and sixth MOS transistors and said second capacitive element being connected in the same manner as the corresponding elements of said first basic circuit, said output terminal of said first basic circuit being connected to one of the main electrodes of said fourth MOS transistor, the gate terminals of said fourth and sixth MOS transistors being capable of receiving third and fourth synchronizing pulses, respectively; said first and second basic circuits being connected alternatingly in a multiplicity of stages so that scanning pulses are successively output from said output terminals of said basic circuits of the successive stages.
Claim 11
Dependent Claim
26 words
A scanning pulse generating circuit as set forth in claim 8, wherein each of said first and second capacitive elements is constituted by a MOS diode.
Claim 12
Dependent Claim
40 words
A scanning pulse generating circuit as set forth in claim 8, wherein only the outputs from the group of said first basic circuits or the outputs from the group of said second basic circuits are used as the scanning pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-25 | 1993-06-26 | 1993-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-25 | 1997-06-26 | 1997-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-25 | 2001-06-26 | 2001-12-26 | $7700.00 | Window Closed / Lapsed |