Field effect transistor logic gate with isolation device for reducing power dissipation

Claim 2

A logical gating circuit having an output comprising, a two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to the other, first phase recurring clock signal, said switch means conducting electrical current therethrough to one terminal of said logical network and to said output for simultaneously applying a voltage level to said one terminal of said logical network and to said output during a first said phase recurring clock signal, said first semiconductor switch means conducting electrical current therethrough only during said first phase recurring clock signal, second semiconductor switch means connected between the other terminal of said logical network and a different voltage level for isolating said other terminal from said different voltage level, and for connecting said second terminal to said different voltage level during a second phase recurring clock signal for enabling the output to change from said first recited voltage level to said different voltage level if an electrical path exists between the terminals of said logical network during said second phase recurring clock signal.

Claim 3

A logical gating circuit having an output comprising, a two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to the other, first field effect transistor means operable for simultaneously applying a voltage level to one terminal of said logical network and to said output during a first phase recurring clock signal, said first field-effect-transistor means operable only during said first phase recurring clock signal, second field-effect-transistor means connected between the other terminal of said logical network and a different voltage level for isolating said other terminal from said different voltage level during said first phase recurring clock signal whereby power dissipated by the circuit is reduced during the first phase recurring clock signal when an electrical path exists between said terminals, said second field-effect-transistor means operable during a second phase recurring clock signal for connecting said other terminal to said different voltage level whereby the output is enabled to change to said different voltage level if an electrical path exists between said terminals.

Claim 4

A logical gating circuit having an output comprising, a two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to the other, first field effect transistor means operable for simultaneously applying a voltage level to one terminal of said logical network and to said output during a first phase recurring clock signal, said first field-effect-transistor means operable only during said first phase recurring clock signal, second field-effect-transistor means connected between the other terminal of said logical network and a different voltage level for isolating said other terminal from said different voltage level during said first phase recurring clock signal whereby power dissipated by the circuit is reduced during the first phase recurring clock signal when an electrical path exists between said terminals, said second field-effect-transistor means operable during a second phase recurring clock signal for connecting said other terminal to said different voltage level whereby the output is enabled to change to said different voltage level if an electrical path exists between said terminals.

Claim 5

The circuit recited in claim 2 wherein said voltage levels each represent a logical state.

Claim 6

The circuit recited in claim 2 wherein a third field-effect-transistor means is connected between said output and said first recited terminal of said logical network, said third field-effect-transistor means being operable said first and second phase recurring clock signals and being rendered nonconductive after said second phase recurring clock signal for isolating said output from said logical network until the recurrence of said first phase recurring clock signal.

Claim 7

A multiphase gate comprising, an output, a second electrode connected to a first voltage level, and a control electrode for rendering said field effect transistor operable to conduct electrical current therethrough during a first phase recurring clock signal for connecting said first voltage level to said output, a logical network having first and second terminals and comprising one or more field effect transistors having one or more control electrodes for receiving input signals, said input signals determining the impedance of an electrical path from one terminal of said network to the other, said first terminal being connected to said output and to said one electrode of said field effect transistor. an isolation field effect transistor having one electrode connected to said second terminal of said logical network, a second electrode connected to a second voltage level; and a control electrode for rendering said isolation field effect transistor operable only during a second phase recurring clock signal.

Claim 8

A multiphase gate comprising, an output, a second electrode connected to a first voltage level, and a control electrode for rendering said field effect transistor operable to conduct electrical current therethrough during a first phase recurring clock signal for connecting said first voltage level to said output, a logical network having first and second terminals and comprising one or more field effect transistors having one or more control electrodes for receiving input signals, said input signals determining the impedance of an electrical path from one terminal of said network to the other, said first terminal being connected to said output and to said one electrode of said field effect transistor. an isolation field effect transistor having one electrode connected to said second terminal of said logical network, a second electrode connected to a second voltage level; and a control electrode for rendering said isolation field effect transistor operable only during a second phase recurring clock signal.

Claim 9

The multiphase gate recited in claim 5 wherein the second electrode and the control electrode of said first recited field effect transistor are connected together and wherein said first phase recurring clock signal applied to said common connection, said first phase recurring clock signal providing said first voltage level to said output.

Claim 10

A logical gate having an output including capacitance for storing a charge, said gate comprising, a two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the impedance of an electrical path from one terminal to the other, first field-effect-transistor means connected between a first terminal of said logical network and a voltage source, said output being connected to a common point between said first field-effect-transistor means and said first terminal, said first field effect transistor operable for applying a first voltage level to said one terminal and to said output during a first phase recurring clock signal, isolation field-effect-transistor means connected between said second terminal and a second voltage level for preventing an electrical path from occurring between said first and second voltage levels during said first phase recurring clock signal and for enabling an electrical path to exist between said output and said second voltage level through said logical network during a second phase recurring clock signal.

Claim 11

A logical gate having an output including capacitance for storing a charge, said gate comprising, a two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the impedance of an electrical path from one terminal to the other, first field-effect-transistor means connected between a first terminal of said logical network and a voltage source, said output being connected to a common point between said first field-effect-transistor means and said first terminal, said first field effect transistor operable for applying a first voltage level to said one terminal and to said output during a first phase recurring clock signal, isolation field-effect-transistor means connected between said second terminal and a second voltage level for preventing an electrical path from occurring between said first and second voltage levels during said first phase recurring clock signal and for enabling an electrical path to exist between said output and said second voltage level through said logical network during a second phase recurring clock signal.

Claim 12

A shift register comprising, a plurality of bit storage positions, each storage position comprising, a first and second half stage, with the first half stage including a first two-terminal logical neTwork comprising one remove field-effect-transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to the other, an output connected to a first one of said terminals, a first field effect transistor connected between a voltage level and said first terminal, said first field effect transistor being operable during a first phase recurring clock signal for simultaneously applying a voltage level to said one terminal of said logical network and to said output, said field-effect-transistor means operable only during said first phase recurring clock signal, a second field effect transistor connected between the other terminal of said logical network and a different voltage level for isolating said other terminal from said different voltage level during said first phase recurring clock signal, for connecting said different voltage level to said second terminal during a second phase recurring clock signal, said second half stage of said shift register comprising, a second two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to another with at least one of said control electrodes connected to the output of said first half stage, an output connected to a first one of the terminals of said second two-terminal logical network, third field effect transistor connected between a voltage level and said first terminal of said second recited logical network, said third field effect transistor operable during a third phase recurring clock signal for simultaneously applying a first voltage level to said one terminal of the second recited logical network and to said output, a fourth field effect transistor connected between the other terminal of said second logical network and a different voltage level for isolating said other terminal from said different voltage level during said third phase recurring clock signal and for connecting said other terminal to said different voltage level during a fourth phase recurring clock signal.

Claim 13

A shift register comprising, a plurality of bit storage positions, each storage position comprising, a first and second half stage, with the first half stage including a first two-terminal logical neTwork comprising one remove field-effect-transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to the other, an output connected to a first one of said terminals, a first field effect transistor connected between a voltage level and said first terminal, said first field effect transistor being operable during a first phase recurring clock signal for simultaneously applying a voltage level to said one terminal of said logical network and to said output, said field-effect-transistor means operable only during said first phase recurring clock signal, a second field effect transistor connected between the other terminal of said logical network and a different voltage level for isolating said other terminal from said different voltage level during said first phase recurring clock signal, for connecting said different voltage level to said second terminal during a second phase recurring clock signal, said second half stage of said shift register comprising, a second two-terminal logical network comprising one or more field effect transistors having one or more control electrodes, the signals on said control electrodes determining the existence of an electrical path from one terminal to another with at least one of said control electrodes connected to the output of said first half stage, an output connected to a first one of the terminals of said second two-terminal logical network, third field effect transistor connected between a voltage level and said first terminal of said second recited logical network, said third field effect transistor operable during a third phase recurring clock signal for simultaneously applying a first voltage level to said one terminal of the second recited logical network and to said output, a fourth field effect transistor connected between the other terminal of said second logical network and a different voltage level for isolating said other terminal from said different voltage level during said third phase recurring clock signal and for connecting said other terminal to said different voltage level during a fourth phase recurring clock signal.