US3676709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four-phase delay element
Assignee: US Philips Corp
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Filing: 1971-05-10
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Granted: 1972-07-11
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Expires: 1991-05-10
Abstract
Abstract A four-phase logic delay circuit using two cascaded stages of field-effect transistors where each stage has two cascaded fieldeffect transistors for the storage of logic signals and two additional field-effect transistors for the isolation of the storage field-effect transistors for the duration of two phases of the four-phase signal.
Inventors
- 👤 Jean Martial Ducamus
- 👤 Claude-Jane Fernandez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
290 words
A four-phase delay element comprising the cascade arrangement of at least a first and a second stage which each include at least a first and a second field-effect transistor, the source of the first transistor being connected to the drain of the second transistor, the drain of the first transistor of the first stage and the gate of the second transistor of the second stage being connected to a storage capacitor, means being provided for applying a logical signal to the gate of the second transistor of the first stage, the drain of the first transistor of the first stage being connected to a first clock-pulse line and the gate of this transistor being connected to a second clock-pulse line, the drain of the first transistor of the second stage being connected to a third clock-pulse line and the gate of this transistor being connected to a fourth clock-pulse line, characterized in that the drain of the second transistor of the first stage is also connected to the third or the fourth clock-pulse line and the drain of the second transistor of the second stage is connected to the first or the second clock-pulse line, means for connecting the source of the second transistor of the first stage to the first or second clock-pulse line and for isolating the source of the second transistor from the second clock-pulse line during the application of clock pulses to the first and second clock-pulse lines and means for connecting the source of the second transistor of the second stage to the third or fourth clock-pulse line and for isolating the second transistor of the second stage from the third clock-pulse line during the application of clockpulses to the third and fourth clock-pulse lines.
Claim 2
Dependent Claim
290 words
A four-phase delay element comprising the cascade arrangement of at least a first and a second stage which each include at least a first and a second field-effect transistor, the source of the first transistor being connected to the drain of the second transistor, the drain of the first transistor of the first stage and the gate of the second transistor of the second stage being connected to a storage capacitor, means being provided for applying a logical signal to the gate of the second transistor of the first stage, the drain of the first transistor of the first stage being connected to a first clock-pulse line and the gate of this transistor being connected to a second clock-pulse line, the drain of the first transistor of the second stage being connected to a third clock-pulse line and the gate of this transistor being connected to a fourth clock-pulse line, characterized in that the drain of the second transistor of the first stage is also connected to the third or the fourth clock-pulse line and the drain of the second transistor of the second stage is connected to the first or the second clock-pulse line, means for connecting the source of the second transistor of the first stage to the first or second clock-pulse line and for isolating the source of the second transistor from the second clock-pulse line during the application of clock pulses to the first and second clock-pulse lines and means for connecting the source of the second transistor of the second stage to the third or fourth clock-pulse line and for isolating the second transistor of the second stage from the third clock-pulse line during the application of clockpulses to the third and fourth clock-pulse lines.
Claim 3
Dependent Claim
76 words
A four-phase delay element as claimed in claim 1, characterized in that the drain of the second transistor of the first stage is connected via the main current path of at least one third field-effect transistor to the third or the fourth clock-pulse line, the drain of the second transistor of the second stage being connected via the main current path of at least one fourth field-effect transistor to the first or the second clock-pulse line.
Claim 4
Dependent Claim
69 words
A four-phase delay element as claimed in claim 1, characterized in that the source of the second transistor of the first stage is connected via the main current path of a field-effect transistor to the first or the second clock-pulse line, the source of the second transistor of the second stage being connected via the main current path of a transistor to the third or the fourth clock-pulse line.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-11 | 1976-01-10 | 1976-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-11 | 1980-01-10 | 1980-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-11 | 1984-01-10 | 1984-07-11 | $7700.00 | Window Closed / Lapsed |