US5212399A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low cost polysilicon active p-channel load
Assignee: Micron Technology Inc
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Filing: 1991-08-15
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Granted: 1993-05-18
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Expires: 2011-08-15
Abstract
Abstract A low cost active P-channel load for use in semiconductor devices is developed. The active P-channel load may be used in a variety of designs, such as functioning as a pullup device in integrated circuits and more specifically for use as a pullup resistor in SRAM devices. The P-channel load is built overlying an active NMOS device and not only takes up less die space but also allows for a simple process to construct the P-channel load. This P-channel device is easily incorporated into an SRAM process flow to build an SRAM cell made up of active NMOS devices that utilize the P-channel devices as pullups.
Inventors
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:39
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
181 words
A structure of an active device combined with an active load, said structure constructed in a semiconductor device fabricated on a starting substrate, said structure comprising: a) said active device having a control gate overlying a substrate portion of first type conductivity and separated therefrom by a gate dielectric layer, said control gate spanning between first and second diffusion regions conductively doped to a second type conductivity; and b) said active load having a lower channel semiconductive material portion of second type conductivity directly overlying and separated from said control gate by a first dielectric layer, an upper channel intrinsic semiconductive material portion aligning and connecting to said lower portion, first and second terminals of first type conductivity lying above said upper portion and extending downward to connect to either side of said upper portion thereby forming a u-shaped junction, said first terminal being separated from said active device's first diffusion region by a second dielectric layer and said second terminal connecting to said active device's second diffusion region at a contact location and separated elsewhere by said second dielectric layer.
Claim 2
Dependent Claim
181 words
A structure of an active device combined with an active load, said structure constructed in a semiconductor device fabricated on a starting substrate, said structure comprising: a) said active device having a control gate overlying a substrate portion of first type conductivity and separated therefrom by a gate dielectric layer, said control gate spanning between first and second diffusion regions conductively doped to a second type conductivity; and b) said active load having a lower channel semiconductive material portion of second type conductivity directly overlying and separated from said control gate by a first dielectric layer, an upper channel intrinsic semiconductive material portion aligning and connecting to said lower portion, first and second terminals of first type conductivity lying above said upper portion and extending downward to connect to either side of said upper portion thereby forming a u-shaped junction, said first terminal being separated from said active device's first diffusion region by a second dielectric layer and said second terminal connecting to said active device's second diffusion region at a contact location and separated elsewhere by said second dielectric layer.
Claim 3
Dependent Claim
13 words
The structure of claim 1, wherein said starting substrate is a silicon wafer.
Claim 4
Dependent Claim
15 words
The structure of claim 1, wherein said semiconductor device is a static random access memory.
Claim 5
Dependent Claim
11 words
The structure of claim 1, wherein said semiconductive material is polysilicon.
Claim 6
Dependent Claim
19 words
The structure of claim 1, wherein said first type conductivity is p-type and said second type conductivity is n-type.
Claim 7
Dependent Claim
19 words
The structure of claim 1, wherein said first type conductivity is n-type and said second type conductivity is p-type.
Claim 8
Dependent Claim
178 words
A semiconductor device fabricated on a starting substrate, having a structure comprising an active device combined with an active load, said structure comprising: a) said active device having a control gate overlying a substrate portion of first type conductivity and separated therefrom by a gate dielectric layer, said control gate spanning between first and second diffusion regions conductively doped to a second type conductivity; and b) said active load having a lower channel semiconductive material portion of second type conductivity directly overlying and separated from said control gate by a first dielectric layer, an upper channel intrinsic semiconductive material portion aligning and connecting to said lower portion, first and second terminals of first type conductivity lying above said upper portion and extending downward to connect to either side of said upper portion thereby forming a u-shaped junction, said first terminal being separated from said active device's first diffusion region by a second dielectric layer and said second terminal connecting to said active device's second diffusion region at a contact location and separated elsewhere by said second dielectric layer.
Claim 9
Dependent Claim
178 words
A semiconductor device fabricated on a starting substrate, having a structure comprising an active device combined with an active load, said structure comprising: a) said active device having a control gate overlying a substrate portion of first type conductivity and separated therefrom by a gate dielectric layer, said control gate spanning between first and second diffusion regions conductively doped to a second type conductivity; and b) said active load having a lower channel semiconductive material portion of second type conductivity directly overlying and separated from said control gate by a first dielectric layer, an upper channel intrinsic semiconductive material portion aligning and connecting to said lower portion, first and second terminals of first type conductivity lying above said upper portion and extending downward to connect to either side of said upper portion thereby forming a u-shaped junction, said first terminal being separated from said active device's first diffusion region by a second dielectric layer and said second terminal connecting to said active device's second diffusion region at a contact location and separated elsewhere by said second dielectric layer.
Claim 10
Dependent Claim
13 words
The structure of claim 7, wherein said starting substrate is a silicon wafer.
Claim 11
Dependent Claim
14 words
The structure of claim 7, wherein said semiconductor device is a random access memory.
Claim 12
Dependent Claim
11 words
The structure of claim 7, wherein said semiconductive material is polysilicon.
Claim 13
Dependent Claim
19 words
The structure of claim 7, wherein said first type conductivity is p-type and said second type conductivity is n-type.
Claim 14
Dependent Claim
19 words
The structure of claim 7, wherein said first type conductivity is n-type and said second type conductivity is p-type.
Claim 15
Dependent Claim
178 words
A structure comprising an active NMOS device combined with an active PMOS load, said structure constructed in a semiconductor device fabricated on a starting silicon substrate, said structure comprising: a) said active NMOS device having a control gate overlying a p-type silicon substrate portion and separated therefrom by a gate dielectric layer, said control gate spanning between source and drain regions; and b) said active PMOS load having a lower channel portion of n-type polysilicon material directly overlying and separated from said control gate by a first dielectric layer, an upper channel portion of intrinsic polysilicon material aligning and connecting to said lower channel portion, first and second terminals of p-type polysilicon lying above said upper channel portion and extending downward to connect to either side of said upper channel portion thereby forming a u-shaped junction, said first terminal being separated from said active NMOS device's source region by a second dielectric layer and said second terminal connected to said active NMOS device's drain region at an intrinsic contact location and separated elsewhere by said second dielectric layer.
Claim 16
Dependent Claim
178 words
A structure comprising an active NMOS device combined with an active PMOS load, said structure constructed in a semiconductor device fabricated on a starting silicon substrate, said structure comprising: a) said active NMOS device having a control gate overlying a p-type silicon substrate portion and separated therefrom by a gate dielectric layer, said control gate spanning between source and drain regions; and b) said active PMOS load having a lower channel portion of n-type polysilicon material directly overlying and separated from said control gate by a first dielectric layer, an upper channel portion of intrinsic polysilicon material aligning and connecting to said lower channel portion, first and second terminals of p-type polysilicon lying above said upper channel portion and extending downward to connect to either side of said upper channel portion thereby forming a u-shaped junction, said first terminal being separated from said active NMOS device's source region by a second dielectric layer and said second terminal connected to said active NMOS device's drain region at an intrinsic contact location and separated elsewhere by said second dielectric layer.
Claim 17
Dependent Claim
15 words
The structure of claim 13, wherein said semiconductor device is a static random access memory.
Claim 18
Dependent Claim
177 words
A static random access semiconductor device fabricated on a silicon substrate, having a structure comprising an active NMOS device combined with an active PMOS load, said structure comprising: a) said active NMOS device having a control gate overlying a p-type silicon substrate portion and separated therefrom by a gate dielectric layer, said control gate spanning between source and drain regions; and b) said active PMOS load having a lower channel portion of n-type polysilicon material directly overlying and separated from said control gate by a first dielectric layer an upper channel portion of intrinsic polysilicon material aligning and connecting to said lower channel portion, first and second terminals of p-type polysilicon lying above said upper channel portion and extending downward to connect to either side of said upper channel portion thereby forming a u-shaped junction, said first terminal being separated from said active NMOS device's source region by a second dielectric layer and said second terminal connected to said active NMOS device's drain region at an intrinsic contact location and separated elsewhere by said second dielectric layer.
Claim 19
Dependent Claim
177 words
A static random access semiconductor device fabricated on a silicon substrate, having a structure comprising an active NMOS device combined with an active PMOS load, said structure comprising: a) said active NMOS device having a control gate overlying a p-type silicon substrate portion and separated therefrom by a gate dielectric layer, said control gate spanning between source and drain regions; and b) said active PMOS load having a lower channel portion of n-type polysilicon material directly overlying and separated from said control gate by a first dielectric layer an upper channel portion of intrinsic polysilicon material aligning and connecting to said lower channel portion, first and second terminals of p-type polysilicon lying above said upper channel portion and extending downward to connect to either side of said upper channel portion thereby forming a u-shaped junction, said first terminal being separated from said active NMOS device's source region by a second dielectric layer and said second terminal connected to said active NMOS device's drain region at an intrinsic contact location and separated elsewhere by said second dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |