High speed transfer of instructions from a master to a slave processor

Claim 2

A first device which is coupled to and receives a plurality of instructions from a second device, said instructions each having an opcode and a set of operands, the first device comprising: a) a first buffer to store each of the opcodes; b) means for moving one of the opcodes from the first buffer to a second buffer when a fist operand in the set of operands associated with the one of the opcodes is delivered to the first device from the second device indicating that the set of operands is valid; c) means for receiving the set of operands from the second device and executing each of the instructions, d) means for receiving a signal from the second device which indicates whether a set of operands is invalid; and e) means for invalidating any opcodes in the first buffer having a set of operands which are identified as invalid by said means for receiving a signal.

Claim 3

A first device according to claim 1, further comprising means for predecoding the opcode in the first buffer, while awaiting a delivery of the set of operands from the second device, said means for predecoding coupled to the first buffer.

Claim 4

A first device according to claim 2 wherein said first device is a vector processor.

Claim 5

A first device according to claim 3 wherein said first buffer is a two opcode deep buffer.

Claim 6

A first device according to claim 4 wherein said second buffer is a one instruction deep buffer holding an opcode and a set of three operands.

Claim 11

A method according to claim 7 wherein the step of operating the scalar processor is carried out by a second micro-engine in the scalar processor.

Claim 12

A method according to claim 8 wherein the step of delivering each valid processed set of operands is preceded by the step of delivering a signal to the vector processor from a third micro-engine in the scalar processor, the signal indicating the scalar processor is ready to deliver the processed set of operands.

Claim 15

A method according to claim 10 wherein the step of moving the opcode is performed upon receiving a first operand in the processed set of operands from the master processor.

Claim 16

A method according to claim 11 wherein the master processor is a scalar processor and the slave processor is a vector processor.

Claim 17

A method according to claim 12 wherein the step of sending the opcode further comprises the step of: operating a first micro-engine in the scalar processor to send a new instruction signal and the opcode to a vector opcode decoder and determining by the vector opcode decoder whether the opcode is for a vector instruction, said vector opcode decoder issuing a new vector instruction signal to the vector processor when the opcode is for a vector instruction, the new vector instruction signal instructing the vector processor to read the opcode from the scalar processor.

Claim 18

A method according to claim 13 wherein the step of operating the master processor is carried out by a second micro-engine in the master processor.

Claim 19

A method according to claim 14 wherein the steps of delivering a signal and determining the occurrence of an exception are carried out by a third micro-engine in the master processor.

Claim 20

A method according to claim 15 wherein the step of moving the opcode further comprises the steps of: i) checking whether the first operand is valid in the second buffer; and ii) sending a valid signal from the second buffer when the first operand is valid to select and move to the second buffer the opcode associated with the processed set of operands.

Claim 21

A method according to claim 16 wherein the step of invalidating any opcodes further comprises the steps of: i. sending the opcode from the first micro-engine to the third micro-engine and receiving the opcode in the third micro-engine; ii. determining whether any other opcodes are present in the third micro-engine and whether any one of the other opcodes is invalid; and iii. sending a flush signal to the vector processor when any one of the other opcodes is invalid.

Claim 22

A method according to claim 17 wherein the step of determining whether any one of the other opcodes is invalid is carried out by the third micro-engine.

Claim 23

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, said instructions each having an opcode and a set of operands, the interface comprising: a) a first micro-engine in the master processor for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means for storing each opcode in a first buffer in the slave processor, the first buffer comprising a two opcode deep buffer; b) a second micro-engine in the master processor for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; c) means for pre-decoding the opcodes in the first buffer by the slave processor while awaiting delivery of the processed sets of operands from the master processor; d) a third micro-engine in the master processor for determining the validity of each set of operands, for delivering a first signal from the master processor to the slave processor indicating the master processor is ready to deliver a valid processed set of operands, for delivering a second signal from the master processor to the slave processor directing the slave processor to discard each opcode whose associated set of operands is not valid; and e) means for delivering the valid processed set of operands to the slave processor, discarding each opcode in the first buffer which is not valid, and executing each of the instructions.

Claim 24

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, said instructions each having an opcode and a set of operands, the interface comprising: a) a first micro-engine in the master processor for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means for storing each opcode in a first buffer in the slave processor, the first buffer comprising a two opcode deep buffer; b) a second micro-engine in the master processor for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; c) means for pre-decoding the opcodes in the first buffer by the slave processor while awaiting delivery of the processed sets of operands from the master processor; d) a third micro-engine in the master processor for determining the validity of each set of operands, for delivering a first signal from the master processor to the slave processor indicating the master processor is ready to deliver a valid processed set of operands, for delivering a second signal from the master processor to the slave processor directing the slave processor to discard each opcode whose associated set of operands is not valid; and e) means for delivering the valid processed set of operands to the slave processor, discarding each opcode in the first buffer which is not valid, and executing each of the instructions.

Claim 25

A master-slave interface according to claim 19 wherein the interface further comprises a second buffer in the slave processor coupled to the first buffer and to the means for delivering the valid processed set of operands, the second buffer functioning to hold the opcode and a processed set of three operands associated therewith.

Claim 26

A scalar-vector processor interface for transferring a plurality of instructions from a scalar processor coupled to a vector processor, the instructions each having an opcode and a set of operands, the interface comprising: a) a first micro-engine, in the scalar processor, for sending the opcode for each of the instructions to be executed from the scalar processor to the vector processor and means, in the vector processor, for storing each opcode in a first buffer in the vector processor; b) a second micro-engine, in the scalar processor, for operating the scalar processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor; c) a third micro-engine, in the scalar processor, for determining the validity of a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor, and, for delivering a signal from the scalar processor to the vector processor indicating the scalar processor is ready to deliver a valid processed set of operands for an instruction; d) means, in the scalar processor, for delivering the valid processed set of operands associated with each opcode sent to the first buffer to a second buffer in the vector processor; e) means, in the vector processor, for moving the opcode, associated with the valid processed set of operands, from the first buffer to the second buffer upon receiving a first operand in the valid processed set of operands from the scalar processor; and f) means for invalidating any opcodes in the first buffer having an associated set of operands which, when fetched and processed by the scalar processor, are determined to be invalid.

Claim 27

A scalar-vector processor interface for transferring a plurality of instructions from a scalar processor coupled to a vector processor, the instructions each having an opcode and a set of operands, the interface comprising: a) a first micro-engine, in the scalar processor, for sending the opcode for each of the instructions to be executed from the scalar processor to the vector processor and means, in the vector processor, for storing each opcode in a first buffer in the vector processor; b) a second micro-engine, in the scalar processor, for operating the scalar processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor; c) a third micro-engine, in the scalar processor, for determining the validity of a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the vector processor, and, for delivering a signal from the scalar processor to the vector processor indicating the scalar processor is ready to deliver a valid processed set of operands for an instruction; d) means, in the scalar processor, for delivering the valid processed set of operands associated with each opcode sent to the first buffer to a second buffer in the vector processor; e) means, in the vector processor, for moving the opcode, associated with the valid processed set of operands, from the first buffer to the second buffer upon receiving a first operand in the valid processed set of operands from the scalar processor; and f) means for invalidating any opcodes in the first buffer having an associated set of operands which, when fetched and processed by the scalar processor, are determined to be invalid.

Claim 28

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, the instructions each having an opcode and a set of operands, the interface comprising: a) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor; b) means, in the master processor, for operating the master processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; c) means, in the master processor, for determining whether an exception has occurred during the fetching and processing of each of the set of operands associated with each opcode stored in the first buffer; d) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction; e) means, in the master processor, for delivering the processed set of operands associated with each opcode sent to the first buffer to a second buffer, in the slave processor; f) means, in the slave processor, for moving the opcode, associated with the processed set of operands, from the first buffer to the second buffer upon receiving the processed set of operands from the master processor; and g) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

Claim 29

A master-slave processor interface for transferring a plurality of instructions from a master processor coupled to a slave processor, the instructions each having an opcode and a set of operands, the interface comprising: a) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor; b) means, in the master processor, for operating the master processor to fetch, from a source of operands, and process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; c) means, in the master processor, for determining whether an exception has occurred during the fetching and processing of each of the set of operands associated with each opcode stored in the first buffer; d) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction; e) means, in the master processor, for delivering the processed set of operands associated with each opcode sent to the first buffer to a second buffer, in the slave processor; f) means, in the slave processor, for moving the opcode, associated with the processed set of operands, from the first buffer to the second buffer upon receiving the processed set of operands from the master processor; and g) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

Claim 30

A master-slave interface according to claim 22 wherein the means for moving the opcode operates upon receiving the first operand in the associated processed set of operands from the master processor.

Claim 31

A master-slave interface according to claim 23 wherein the master processor is a scalar processor and the slave processor is a vector processor.

Claim 32

A master-slave interface according to claim 24 wherein the means for sending the opcode is a first micro-engine in the master processor.

Claim 33

A master-slave interface according to claim 25 wherein the means for operating the master processor is a second micro-engine in the master processor.

Claim 34

A master-slave interface according to claim 26 wherein the means for delivering a signal is a third micro-engine in the master processor.

Claim 35

A master-slave interface according to claim 27 wherein the means for moving the opcode, further comprises: i) means for checking whether the first operand is valid in the second buffer; and ii) means for sending a valid signal from the second buffer to the first buffer when the first operand is valid to select and move to the second buffer the opcode associated with the processed set of operands.

Claim 36

A master-slave interface according to claim 28 wherein the means for invalidating any opcodes, further comprises: i) means for receiving the opcode from the first micro-engine in the third micro-engine; ii) means for determining whether any other opcodes are present in the third micro-engine and whether any one of the other opcodes is invalid; and iii) means for sending a flush signal to the vector processor if the any one of the other opcodes is invalid.

Claim 37

A master-slave interface according to claim 29 wherein the means for determining whether any one of the other opcodes is invalid is carried out by the third micro-engine.

Claim 38

A master-slave interface according to claim 30 wherein the first buffer is a two opcode deep buffer.

Claim 39

A master-slave interface according to claim 31 wherein the second buffer is a one instruction deep buffer holding an opcode and a set of three operands.

Claim 40

A computer system, comprising: a) a master processor for transferring a plurality of instructions, the instructions each having an opcode and a set of operands; b) a slave processor, coupled to the master processor, for receiving and executing the plurality of instructions; c) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor; d) means, in the master processor, for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; e) means, coupled to the first buffer, for pre-decoding the opcodes in the first buffer by the slave processor while awaiting a delivery of the processed set of operands from the master processor; f) means, in the master processor, for determining whether an exception occurred during the fetching and processing of the set of operands; g) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction; h) means, in the master processor, for delivering a processed set of operands to a second buffer in the slave processor; i) means, in the slave processor, for moving the opcode associated with each processed set of operands from the first buffer to the second buffer upon receiving the processed sets of operands from the master processor; and j) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

Claim 41

A computer system, comprising: a) a master processor for transferring a plurality of instructions, the instructions each having an opcode and a set of operands; b) a slave processor, coupled to the master processor, for receiving and executing the plurality of instructions; c) means, in the master processor, for sending the opcode for each of the instructions to be executed from the master processor to the slave processor and means, in the slave processor, for storing the opcode in a first buffer in the slave processor; d) means, in the master processor, for operating the master processor to fetch, from a source of operands, and to process a set of operands associated with each opcode sent to the first buffer for each of the instructions to be executed by the slave processor; e) means, coupled to the first buffer, for pre-decoding the opcodes in the first buffer by the slave processor while awaiting a delivery of the processed set of operands from the master processor; f) means, in the master processor, for determining whether an exception occurred during the fetching and processing of the set of operands; g) means, in the master processor, for delivering a signal from the master processor to the slave processor indicating the master processor is ready to deliver a processed set of operands for an instruction; h) means, in the master processor, for delivering a processed set of operands to a second buffer in the slave processor; i) means, in the slave processor, for moving the opcode associated with each processed set of operands from the first buffer to the second buffer upon receiving the processed sets of operands from the master processor; and j) means, in the master processor, for invalidating any opcodes in the first buffer having an associated set of operands which are being fetched and processed by the master processor when an exception occurs.

Claim 42

A computer system according to claim 33 wherein the means for moving the opcode operates upon receiving a first operand in a set of operands from the master processor.

Claim 43

A computer system according to claim 34 wherein the master processor is a scalar processor and the slave processor is a vector processor.

Claim 44

A computer system according to claim 35 wherein the means for sending the opcode is a first micro-engine in the master processor.

Claim 45

A computer system according to claim 36 wherein the means for operating the master processor is a second micro-engine in the master processor.

Claim 46

A computer system according to claim 37 wherein the means for delivering a signal is a third micro-engine in the master processor.

Claim 47

A computer system according to claim 38 wherein the first buffer is a two opcode deep buffer.

Claim 48

A computer system according to claim 39 wherein the second buffer is a one instruction deep buffer holding an opcode and a set of three operands.