US4803620A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-processor system responsive to pause and pause clearing instructions for instruction execution control
Assignee: Hitachi Ltd
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Filing: 1987-01-05
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Granted: 1989-02-07
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Expires: 2007-01-05
Abstract
Abstract A multi-processor system including a main storage for storing instructions and data, a master processor for supplying to a slave processor data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further operating to test the operation state of the slave processor and perform processing by utilizing the result of the processing executed by the slave processor. The slave processor initiates the processing under the command of the master processor and operates to inform of the master processor of completion of the processing. The slave processor operates to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator of the slave processor. When the pause indication is set in the slave processor, the master processor operates to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The slave processor also operates to set at the indicator an indication instruction indicating completion of execution of the succedding instruction. The master processor functions to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.
Inventors
- 👤 Yasuhiro Inagami
- 👤 Takayuki Nakagawa
- 👤 Shigeo Nagashima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:31
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
374 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoded instruction; indication means connected to said activation control means for indicating thereto an operation state of said first processor; a registration control means connected to respond to decoding of a pause instruction by said first decoding means for setting at said indication means a pause indication indicating that said first processor is in a pause state; said first activating control means including means connected to respond to said pause indication for suspending activation of a succeeding instruction decoded after the pause instruction so long as said pause indication is issued by said indication means; said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register for decoding the instruction held by said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded by said second decoding means; said registration control means including means connected to said second decoding means and responsive to decoding of a pause clearing instruction by said second decoding means and to indication of a pause state by said indication means for resetting said pause indication and for supplying to said second activation control means a completion signal indicating that said pause indication has been reset and responsive to the decoding of a pause clearing instruction and to indication of a non-pause state by said indication means for supplying to said second activation control means an incompletion signal; and said second activation control means including means responsive to said incompletion signal for suspending activation of a succeeding instruction decoded after decoding of the pause clearing instruction by said second decoding means until said completion signal is received by said second activation control means.
Claim 2
Dependent Claim
374 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoded instruction; indication means connected to said activation control means for indicating thereto an operation state of said first processor; a registration control means connected to respond to decoding of a pause instruction by said first decoding means for setting at said indication means a pause indication indicating that said first processor is in a pause state; said first activating control means including means connected to respond to said pause indication for suspending activation of a succeeding instruction decoded after the pause instruction so long as said pause indication is issued by said indication means; said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register for decoding the instruction held by said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded by said second decoding means; said registration control means including means connected to said second decoding means and responsive to decoding of a pause clearing instruction by said second decoding means and to indication of a pause state by said indication means for resetting said pause indication and for supplying to said second activation control means a completion signal indicating that said pause indication has been reset and responsive to the decoding of a pause clearing instruction and to indication of a non-pause state by said indication means for supplying to said second activation control means an incompletion signal; and said second activation control means including means responsive to said incompletion signal for suspending activation of a succeeding instruction decoded after decoding of the pause clearing instruction by said second decoding means until said completion signal is received by said second activation control means.
Claim 3
Dependent Claim
38 words
A multi-processor system according to claim 1, wherein said indication means of said first processor includes a storage area for indication of the operating state within a register for holding a program status word for said first processor.
Claim 4
Dependent Claim
355 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying to said first processor data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoding instruction; indication means connected to said first activation control means for indicating thereto an operation state of said first processor; register means connected to said first decoding means and responsive to the decoding of an indication instruction wherein said indication instruction causes decoded information of a succeeding instruction to be temporarily stored in said register means; detect means for detecting completion of execution of the succeeding instruction, registration control means connected to respond to said detect means for setting at said indication means an indication of execution completion; and said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register and said registration control means for decoding the instruction held in said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded thereby; said registration control means including means responsive to decoding of an indication resetting instruction by said second decoding means and indication of execution completion by said indication means for resetting said execution completion indication and for supplying said second activation control means with a completion signal indicating that said indication of execution completion has been reset and responsive to the decoding of an indication resetting instruction and indication of a non-execution completion state by said indication means for supplying to said second activation control means an incompletion signal; said second activation control means being responsive to said incompletion signal to thereby suspend activation of a succeeding instruction decoded after the indication resetting instruction by said second decoding means until said completed signal is received.
Claim 5
Dependent Claim
355 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying to said first processor data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoding instruction; indication means connected to said first activation control means for indicating thereto an operation state of said first processor; register means connected to said first decoding means and responsive to the decoding of an indication instruction wherein said indication instruction causes decoded information of a succeeding instruction to be temporarily stored in said register means; detect means for detecting completion of execution of the succeeding instruction, registration control means connected to respond to said detect means for setting at said indication means an indication of execution completion; and said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register and said registration control means for decoding the instruction held in said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded thereby; said registration control means including means responsive to decoding of an indication resetting instruction by said second decoding means and indication of execution completion by said indication means for resetting said execution completion indication and for supplying said second activation control means with a completion signal indicating that said indication of execution completion has been reset and responsive to the decoding of an indication resetting instruction and indication of a non-execution completion state by said indication means for supplying to said second activation control means an incompletion signal; said second activation control means being responsive to said incompletion signal to thereby suspend activation of a succeeding instruction decoded after the indication resetting instruction by said second decoding means until said completed signal is received.
Claim 6
Dependent Claim
73 words
A multi-processor system according to claim 3, wherein said first processor is a vector processor, and said means for identifying completion of the succeeding instruction includes second storing means for storing the result of decoding of said succeeding instruction, and comparison means for comparing the content stored in said second storing means with the information concerning the execution completion of said succeeding instruction to thereby identify the execution completion of said succeeding instruction.
Claim 7
Dependent Claim
34 words
A multi-processor system according to claim 3, wherein said indication means includes a storage area for indication of the operating state within a register for holding a program status word for said first processor.
Claim 8
Dependent Claim
514 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoded instruction; indication means connected to said activation control means for indicating thereto an operation state of said first processor; first registration control means connected to respond to decoding of a pause instruction by said first decoding means for setting at said indication means a pause indication indicating that said first processor is in a pause state, and said first activation control means including means connected to respond to said pause indication for suspending activation of a succeeding instruction decoded after the pause instruction so long as said pause indication is issued by said indication means; register means connected to said first decoding means for storing temporarily an indication command resulting from the decoding of an indication instruction; detect means for identifying completion of execution of the succeeding instruction, and second registration control means connected to respond to said detect means for setting at said indication means an indication of execution completion; and said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register and said first and second registration control means for decoding the instruction held in said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded thereby; said first registration control means including means responsive to decoding of a pause clearing instruction by said second decoding means and to indication of a pause state by said indication means for resetting said pause indication and for supplying said second activation control means with a completion responsive to the decoding of a pause clearing instruction and : to indication of a non-pause state by said indication means for supplying said second activation control means with an incompletion signal; said second registration control means including means responsive to decoding of an indication resetting instruction by said second decoding means and to indication of execution completion by said indication means for resetting execution completion indication and for supplying said second activation control means with a completion signal indicating that said indication of execution completion has been reset and responsive to the decoding of the indication resetting instruction and indication of a non-execution completion state by said indication means for supplying said second activation control means with said incompletion signal; said second activation control means responding to said incompletion signal either from said first or second registration control means to thereby suspend activation of a succeeding instruction decoded after decoding of the clearing instruction or indication resetting instruction by said second decoding means until said completion signal is received.
Claim 9
Dependent Claim
514 words
A multi-processor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor; said first processor including a first instruction register for holding an instruction to be executed thereby; first decoding means connected to said first instruction register for decoding the instruction held by said first instruction register; first activation control means connected to said first decoding means for controlling activation of the decoded instruction; indication means connected to said activation control means for indicating thereto an operation state of said first processor; first registration control means connected to respond to decoding of a pause instruction by said first decoding means for setting at said indication means a pause indication indicating that said first processor is in a pause state, and said first activation control means including means connected to respond to said pause indication for suspending activation of a succeeding instruction decoded after the pause instruction so long as said pause indication is issued by said indication means; register means connected to said first decoding means for storing temporarily an indication command resulting from the decoding of an indication instruction; detect means for identifying completion of execution of the succeeding instruction, and second registration control means connected to respond to said detect means for setting at said indication means an indication of execution completion; and said second processor including a second instruction register for holding an instruction to be executed thereby; second decoding means connected to said second instruction register and said first and second registration control means for decoding the instruction held in said second instruction register; and second activation control means connected to said second decoding means for controlling activation of the instruction decoded thereby; said first registration control means including means responsive to decoding of a pause clearing instruction by said second decoding means and to indication of a pause state by said indication means for resetting said pause indication and for supplying said second activation control means with a completion responsive to the decoding of a pause clearing instruction and : to indication of a non-pause state by said indication means for supplying said second activation control means with an incompletion signal; said second registration control means including means responsive to decoding of an indication resetting instruction by said second decoding means and to indication of execution completion by said indication means for resetting execution completion indication and for supplying said second activation control means with a completion signal indicating that said indication of execution completion has been reset and responsive to the decoding of the indication resetting instruction and indication of a non-execution completion state by said indication means for supplying said second activation control means with said incompletion signal; said second activation control means responding to said incompletion signal either from said first or second registration control means to thereby suspend activation of a succeeding instruction decoded after decoding of the clearing instruction or indication resetting instruction by said second decoding means until said completion signal is received.
Claim 10
Independent Claim
198 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: setting an indication of a pause state of said first processor in response to decoding and execution of a pause instruction by said first processor, and suspending activation of a succeeding instruction in said first processor decoded after decoding and execution of the pause instruction until said indication of a pause state is reset; and resetting said indication of a pause state in said first processor by said second processor in response to decoding and execution of a pause clearing instruction by said second processor supplying from said first processor to said second processor either a completion signal indicating that said pause state has been reset in said first processor or an incompletion signal indicating that said pause state has not been reset in said first processor; and causing said second processor to suspend activation of a succeeding instruction after the pause clearing instruction in said second processor until said completion signal is received.
Claim 11
Independent Claim
198 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: setting an indication of a pause state of said first processor in response to decoding and execution of a pause instruction by said first processor, and suspending activation of a succeeding instruction in said first processor decoded after decoding and execution of the pause instruction until said indication of a pause state is reset; and resetting said indication of a pause state in said first processor by said second processor in response to decoding and execution of a pause clearing instruction by said second processor supplying from said first processor to said second processor either a completion signal indicating that said pause state has been reset in said first processor or an incompletion signal indicating that said pause state has not been reset in said first processor; and causing said second processor to suspend activation of a succeeding instruction after the pause clearing instruction in said second processor until said completion signal is received.
Claim 12
Independent Claim
211 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: identifying completion of execution of an instruction succeeding an execution completion indication instruction in response to decoding and execution of the execution completion indication instruction included in instructions to be executed by said first processor, and setting an indication of execution completion of said succeeding instruction; and resetting said execution completion indication in said first processor by said second processor, in response to decoding and execution of an indication resetting instruction included in instructions to be executed by said second processor and the indication of execution completion, supplying from said first processor to said second processor either a completion signal indicating that said indication of execution completion has been reset in response to decoding and execution of the indication resetting instruction and resetting of execution completion indication or an incompletion signal in response to decoding and execution of an indication resetting instruction and non-execution completion indication; and suspending activation of a succeeding instruction after the resetting instruction in said second processor until said completion signal is received.
Claim 13
Independent Claim
211 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: identifying completion of execution of an instruction succeeding an execution completion indication instruction in response to decoding and execution of the execution completion indication instruction included in instructions to be executed by said first processor, and setting an indication of execution completion of said succeeding instruction; and resetting said execution completion indication in said first processor by said second processor, in response to decoding and execution of an indication resetting instruction included in instructions to be executed by said second processor and the indication of execution completion, supplying from said first processor to said second processor either a completion signal indicating that said indication of execution completion has been reset in response to decoding and execution of the indication resetting instruction and resetting of execution completion indication or an incompletion signal in response to decoding and execution of an indication resetting instruction and non-execution completion indication; and suspending activation of a succeeding instruction after the resetting instruction in said second processor until said completion signal is received.
Claim 14
Independent Claim
357 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: setting indication of a pause state of said first processor in response to decoding and execution of a pause instruction included in instructions to be executed by said first processor, and suspending activation of a succeeding instruction decoded after the decoding and execution of the pause instruction until said indication of a pause state is set; resetting said indication of a pause state in said first processor by said second processor in response to decoding and execution of a pause clearing instruction , by said second processor supplying from said first processor to said second processor either a completion signal indicating that said pause state has been reset in said first processor or an incompletion signal indicating that said pause state has not been reset; and causing said second processor to suspend activation of a succeeding instruction after the clearing instruction in said second processor until said completion signal is received; identifying completion of execution of the instruction succeeding an execution completion indication instruction in response to decoding and execution of the execution completion indication instruction included in instruction to be executed by said first processor, and setting an indication of execution completion of said succeeding instruction; and resetting said execution completion indication in said first processor by said second processor, in response to decoding and execution of an indication resetting instruction included in indication of execution completion, and supplying from said first processor to said second processor either a completion signal indicating that said indication of execution completion has been reset in response to decoding and execution of the indication resetting instruction and resetting of said indication of execution completion or an incompletion signal in response to decoding and execution of the indication resetting instruction and indication of non-execution completion to thereby suspend activation of a succeeding instruction after the resetting, instruction in said second processor until said completion signal is received.
Claim 15
Independent Claim
357 words
A method of executing instructions in a multiprocessor system comprising a first processor and a second processor connected to said first processor for supplying said first processor with data required for execution of instructions by said first processor, said method comprising the steps of: setting indication of a pause state of said first processor in response to decoding and execution of a pause instruction included in instructions to be executed by said first processor, and suspending activation of a succeeding instruction decoded after the decoding and execution of the pause instruction until said indication of a pause state is set; resetting said indication of a pause state in said first processor by said second processor in response to decoding and execution of a pause clearing instruction , by said second processor supplying from said first processor to said second processor either a completion signal indicating that said pause state has been reset in said first processor or an incompletion signal indicating that said pause state has not been reset; and causing said second processor to suspend activation of a succeeding instruction after the clearing instruction in said second processor until said completion signal is received; identifying completion of execution of the instruction succeeding an execution completion indication instruction in response to decoding and execution of the execution completion indication instruction included in instruction to be executed by said first processor, and setting an indication of execution completion of said succeeding instruction; and resetting said execution completion indication in said first processor by said second processor, in response to decoding and execution of an indication resetting instruction included in indication of execution completion, and supplying from said first processor to said second processor either a completion signal indicating that said indication of execution completion has been reset in response to decoding and execution of the indication resetting instruction and resetting of said indication of execution completion or an incompletion signal in response to decoding and execution of the indication resetting instruction and indication of non-execution completion to thereby suspend activation of a succeeding instruction after the resetting, instruction in said second processor until said completion signal is received.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |