Logic circuit including variable impedance means

Claim 2

A logic circuit comprising: first and second terminals for receiving first and second supply voltages, respectively; a first input terminal for receiving an input signal; an output terminal; a first input bipolar transistor having a base coupled to receive the input signal, a collector and an emitter; first variable impedance means coupled between the first terminal and the collector of the first input bipolar transistor and responsive to the input signal and for changing its impedance thereof; second variable impedance means coupled between the emitter of the first input bipolar transistor and the second terminal and for changing its impedance thereof in response to an output signal on the output terminal; an output bipolar transistor having a base coupled to the collector of the first input bipolar transistor and an emitter-collector path coupled between the first terminal and the output terminal; and pull-down means coupled between the output terminal and the second terminal and responsive to an emitter signal on the emitter of the first input bipolar transistor and for pulling down a voltage on the output terminal.

Claim 3

A logic circuit according to claim 1, wherein the first variable impedance means includes: a first P-channel MOSFET having a source-drain path coupled between the first terminal and the collector of the first input bipolar transistor and a gate coupled to the first input terminal, and a diode coupled between the first terminal and the collector of the first input bipolar transistor.

Claim 4

A logic circuit according to claim 2, wherein the first variable impedance means further includes a resistor coupled between the diode and the collector of the first input bipolar transistor.

Claim 5

A logic circuit according to claim 1, wherein the second variable impedance means includes an N-channel MOSFET having a source-drain path coupled between the emitter of the first input bipolar transistor and the second terminal and a gate coupled to the output terminal.

Claim 6

A logic circuit according to claim 2, wherein the pull-down means includes a pull-down bipolar transistor having a collector-emitter path coupled between the output terminal and the second terminal and a base, and wherein the logic circuit further comprises a capacitor coupled between the emitter of the first input bipolar transistor and the base of the pull-down bipolar transistor.

Claim 7

A logic circuit according to claim 5, further comprising: resistor means coupled between the base of the pull-down transistor and the second terminal; and a bias transistor having a collector-emitter path coupled between the first terminal and the base of the pull-down transistor and a base coupled to receive a predetermined voltage.

Claim 8

A logic circuit according to claim 6, wherein the resistor means includes an MOSFET having a source-drain path coupled between the base of the pull-down transistor and the second terminal and a gate coupled to the collector of the first input bipolar transistor.

Claim 9

A logic circuit according to claim 2, wherein the pull-down means includes a pull-down MOSFET having a source-drain path coupled between the output terminal and the second terminal and a gate coupled to the emitter of the first input bipolar transistor.

Claim 10

A logic circuit according to claim 2, further comprising: a second input terminal; a second input bipolar transistor having a collector-emitter path coupled to the collector-emitter path of the first input bipolar transistor in parallel and a base coupled to the second input terminal; and a second P-channel MOSFET having a gate coupled to the second input terminal (S2) and a source-drain path coupled in series to the source-drain path of the first P-channel MOSFET.

Claim 11

A logic circuit according to claim 2, wherein the first input bipolar transistor and the output bipolar transistor are of an NPN type.

Claim 12

A logic circuit according to claim 10, wherein the logic circuit is formed on a semiconductor substrate.

Claim 13

A logic circuit comprising: first and second terminals for receiving first and second supply voltages, respectively; a first input terminal for receiving an input signal; an output terminal; a first input bipolar transistor having a base coupled to receive the input signal, a collector and an emitter; a differentiation circuit coupled to the output terminal; first variable impedance means coupled between the first terminal and the collector of the first input bipolar transistor and responsive to the input signal and for changing its impedance; second variable impedance means coupled between the emitter of the first input bipolar transistor and the second terminal and for changing its impedance in response to an output signal of the differentiation circuit; an output bipolar transistor having a base coupled to the collector of the first input bipolar transistor and an emitter-collector path coupled between the first terminal and the output terminal; and pull-down means coupled between the output terminal and the second terminal and responsive to an emitter signal on the emitter of the first input bipolar transistor and for pulling down a voltage on the output terminal.

Claim 14

A logic circuit comprising: first and second terminals for receiving first and second supply voltages, respectively; a first input terminal for receiving an input signal; an output terminal; a first input bipolar transistor having a base coupled to receive the input signal, a collector and an emitter; a differentiation circuit coupled to the output terminal; first variable impedance means coupled between the first terminal and the collector of the first input bipolar transistor and responsive to the input signal and for changing its impedance; second variable impedance means coupled between the emitter of the first input bipolar transistor and the second terminal and for changing its impedance in response to an output signal of the differentiation circuit; an output bipolar transistor having a base coupled to the collector of the first input bipolar transistor and an emitter-collector path coupled between the first terminal and the output terminal; and pull-down means coupled between the output terminal and the second terminal and responsive to an emitter signal on the emitter of the first input bipolar transistor and for pulling down a voltage on the output terminal.

Claim 15

A logic circuit according to claim 12, wherein the first variable impedance means includes: a first P-channel MOSFET having a source-drain path coupled between the first terminal and the collector of the first input bipolar transistor and a gate coupled to the first input terminal, and a diode coupled between the first terminal and the collector of the first input bipolar transistor.

Claim 16

A logic circuit according to claim 13, wherein the first variable impedance means further includes a resistor coupled between the diode and the collector of the first input bipolar transistor.

Claim 17

A logic circuit according to claim 12, wherein the second variable impedance means includes an N-channel MOSFET having a source-drain path coupled between the emitter of the first input bipolar transistor and the second terminal and a gate coupled to receive the output signal of the differentiation circuit.

Claim 18

A logic circuit according to claim 13, wherein the pull-down means includes a pull-down bipolar transistor having a collector-emitter path coupled between the output terminal and the second terminal and a base, and wherein the logic circuit further comprises a capacitor coupled between the emitter of the first input bipolar transistor and the base of the pull-down bipolar transistor.

Claim 19

A logic circuit according to claim 16, further comprising: resistor means coupled between the base of the pull-down transistor and the second terminal; and a bias transistor having a collector-emitter path coupled between the first terminal and the base of the pull-down transistor and a base coupled to receive a predetermined voltage.

Claim 20

A logic circuit according to claim 13, further comprising: a second input terminal; a second input bipolar transistor having a collector-emitter path coupled in parallel to the collector-emitter path of the first input bipolar transistor and a base coupled to the second input terminal; and a second P-channel MOSFET having a gate coupled to the second input terminal and a source-drain path coupled in series to the source-drain path of the first P-channel MOSFET.

Claim 21

A logic circuit according to claim 13, wherein the first input bipolar transistor and the output bipolar transistor are of an NPN type.

Claim 22

A logic circuit according to claim 19, wherein the logic circuit is formed on a semiconductor substrate.

Claim 23

A logic circuit according to claim 12, wherein the differentiation circuit is coupled between the output terminal and a third terminal to which a predetermined voltage is supplied, wherein the differentiation circuit comprises a resistor and a capacitor coupled in series between the output terminal and the third terminal, and wherein the output signal of the differentiation circuit is provided from a common connection point of the resistor and the capacitor.

Claim 24

A logic circuit comprising: first and second terminals for receiving first and second supply voltages, respectively; a first input terminal for receiving a first input signal; a second input terminal for receiving a second input signal reversed relative to the first input signal; an output terminal; a first input bipolar transistor having a base coupled to receive the input signal, a collector and an emitter; first variable impedance means coupled between the first terminal and the collector of the first input bipolar transistor and responsive to the first input signal and for changing its impedance second variable impedance means coupled between the emitter of the first input bipolar transistor and the second terminal and for changing its impedance in response to the second input signal; an output bipolar transistor having a base coupled to the collector of the first input bipolar transistor and an emitter-collector path coupled between the first terminal and the output terminal; and pull-down means coupled between the output terminal and the second terminal and responsive to an emitter signal on the emitter of the first input bipolar transistor and for pulling down a voltage on the output terminal.

Claim 25

A logic circuit comprising: first and second terminals for receiving first and second supply voltages, respectively; a first input terminal for receiving a first input signal; a second input terminal for receiving a second input signal reversed relative to the first input signal; an output terminal; a first input bipolar transistor having a base coupled to receive the input signal, a collector and an emitter; first variable impedance means coupled between the first terminal and the collector of the first input bipolar transistor and responsive to the first input signal and for changing its impedance second variable impedance means coupled between the emitter of the first input bipolar transistor and the second terminal and for changing its impedance in response to the second input signal; an output bipolar transistor having a base coupled to the collector of the first input bipolar transistor and an emitter-collector path coupled between the first terminal and the output terminal; and pull-down means coupled between the output terminal and the second terminal and responsive to an emitter signal on the emitter of the first input bipolar transistor and for pulling down a voltage on the output terminal.

Claim 26

A logic circuit according to claim 22, wherein the first variable impedance means includes: a first P-channel MOSFET having a source-drain path coupled between the first terminal and the collector of the first input bipolar transistor and a gate coupled to the first input terminal, and a diode coupled between the first terminal and the collector of the first input bipolar transistor.

Claim 27

A logic circuit according to claim 23, wherein the first variable impedance means further includes a resistor coupled between the diode and the collector of the first input bipolar transistor.

Claim 28

A logic circuit according to claim 22, wherein the second variable impedance means includes an N-channel MOSFET having a source-drain path coupled between the emitter of the first input bipolar transistor and the second terminal and a gate coupled to the second input terminal.

Claim 29

A logic circuit according to claim 23, wherein the pull-down means includes a pull-down bipolar transistor having a collector-emitter path coupled between the output terminal and the second terminal and a base, and wherein the logic circuit further comprises a capacitor coupled between the emitter of the first input bipolar transistor and the base of the pull-down bipolar transistor.

Claim 30

A logic circuit according to claim 26, further comprising: resistor means coupled between the base of the pull-down transistor and the second terminal; and a bias transistor having a collector-emitter path coupled between the first terminal and the base of the pull-down transistor and a base coupled to receive a predetermined voltage.

Claim 31

A logic circuit according to claim 27, wherein the resistor means includes an MOSFET having a source-drain path coupled between the base of the pull-down transistor and the second terminal and a gate coupled to the collector of the first input bipolar transistor.

Claim 32

A logic circuit according to claim 23, wherein the pull-down means includes a pull-down MOSFET having a source-drain path coupled between the output terminal and the second terminal and a gate coupled to the emitter of the first input bipolar transistor.

Claim 33

A logic circuit according to claim 23, further comprising: a second input terminal; a second input bipolar transistor having a collector-emitter path coupled to the collector-emitter path of the first input bipolar transistor in parallel and a base coupled to the second input terminal; and a second P-channel MOSFET having a gate coupled to the second input terminal and a source-drain path coupled in series to the source-drain path of the first P-channel MOSFET.

Claim 34

A logic circuit according to claim 22, wherein the first input bipolar transistor and the output bipolar transistor are of an NPN type.

Claim 35

A logic circuit according to claim 31, wherein the logic circuit is formed on a semiconductor substrate.