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US5059836A Expired / Lapsed US ⏱️ 0.0 years remaining

Differential-time-constant bandpass filter using the analog properties of digital circuits

Assignee: Dallas Semiconductor Corp
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Filing: 1990-10-30
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Granted: 1991-10-22
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Expires: 2010-10-30
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Abstract

Abstract An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff-frequency has its output connected to the clock input of a counter.

Inventors

  • 👤 Robert D. Lee
  • 👤 Robert W. Mounger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 18:03
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0225; H04W52/0229; H04W52/0241; Y; Y02; Y02D; Y02D30/00; Y02D30/70

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 240 words
An integrated circuit bandpass filter, for providing a passband with predetermined upper and lower passband edge frequencies, comprising: a first digital circuit which has an input and an output, said first circuit outputting a signal made from delaying by a first time interval first polarity transitions of an input signal but not delaying transitions of polarity opposite said first polarity wherein said first circuit outputs a constant signal if said delayed first polarity transitions overlap said not delayed opposite polarity transitions; a second digital circuit which has an input and an output, said second circuit outputting a signal made from delaying by a first time interval second polarity transitions of an input signal but not delaying transitions of polarity opposite said second polarity wherein said first circuit outputs a constant signal if said delayed second polarity transitions overlap said not delayed opposite polarity transitions; the output of said second circuit connected to the input of said first circuit; a digital counter circuit, having reset and clock inputs, and having a count output which is determined in accordance with said clock and reset inputs; wherein the output of said first digital circuit is connected to drive said reset input of said counter, and the output of said second digital circuit is connected to drive said clock input of said counter; whereby said count output of said counter provides said bandpass filter function for signals at said input of said second circuit.
Claim 2
Dependent Claim 240 words
An integrated circuit bandpass filter, for providing a passband with predetermined upper and lower passband edge frequencies, comprising: a first digital circuit which has an input and an output, said first circuit outputting a signal made from delaying by a first time interval first polarity transitions of an input signal but not delaying transitions of polarity opposite said first polarity wherein said first circuit outputs a constant signal if said delayed first polarity transitions overlap said not delayed opposite polarity transitions; a second digital circuit which has an input and an output, said second circuit outputting a signal made from delaying by a first time interval second polarity transitions of an input signal but not delaying transitions of polarity opposite said second polarity wherein said first circuit outputs a constant signal if said delayed second polarity transitions overlap said not delayed opposite polarity transitions; the output of said second circuit connected to the input of said first circuit; a digital counter circuit, having reset and clock inputs, and having a count output which is determined in accordance with said clock and reset inputs; wherein the output of said first digital circuit is connected to drive said reset input of said counter, and the output of said second digital circuit is connected to drive said clock input of said counter; whereby said count output of said counter provides said bandpass filter function for signals at said input of said second circuit.
Claim 3
Dependent Claim 14 words
The integrated circuit of claim 1, wherein said first digital circuit is an inverter.
Claim 4
Dependent Claim 14 words
The integrated circuit of claim 1, wherein said second digital circuit is an inverter.
Claim 5
Dependent Claim 31 words
The integrated circuit of claim 1, wherein said first and second digital circuits are inverters, and further comprising a capacitor connected in parallel with the output of said first digital circuit.
Claim 6
Dependent Claim 31 words
The integrated circuit of claim 1, wherein said first and second digital circuits are inverters, and further comprising a resistor connected in series with the output of said first digital circuit.
Claim 7
Dependent Claim 39 words
The integrated circuit of claim 1, wherein said first and second digital circuits are inverters, and wherein the input to said first digital circuit has a longer RC time constant than does the input to said second digital circuit.
Claim 8
Dependent Claim 25 words
The filter of claim 1, wherein: said first polarity transitions are high to low transitions; and said second polarity transitions are high to low transitions.
Claim 9
Dependent Claim 17 words
The filter of claim 1, wherein: said first time interval is less than said second time interval.

References Cited (Backward Citations)

US4241311A Cited
US4442500A Cited
US4578653A Cited
US4791379A Cited
US4786823A Cited
US4967108A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-10-21 1995-04-22 1995-10-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-10-21 1999-04-22 1999-10-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-10-21 2003-04-22 2003-10-22 $7700.00 Window Closed / Lapsed

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