Differential-time-constant bandpass filter using the analog properties of digital circuits

Claim 2

An integrated circuit for providing a filter function with predetermined edge frequencies, comprising: a first logic gate which has an input and an output, said output responding with a first predetermined time constant to signals applied at said respective input; a second logic gate which has an input and an output, said output responding with a second predetermined time constant, which is longer than said first time constant, to signals applied at said respective input; and a digital circuit which comprises input connections including at least a clock input and a reset input, and which provides a count output in accordance with said clock and reset inputs; wherein the output of said first logic gate is connected to drive said clock input of said digital circuit, and the output of said second logic gate is connected to drive said reset input of said digital circuit; said respective inputs of said first and second logic gate being commonly connected to receive an external signal; whereby said count output provides a filtered signal generally corresponding to said external signal.

Claim 3

An integrated circuit bandpass filter, for providing a passband with predetermined upper and lower passband edge frequencies, comprising: a first digital circuit which has an input and an output, said output responding with loss-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the lower passband edge frequency, to signals applied at the input thereof; a second digital circuit which has an input and an output, said output responding with low-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the upper passband edge frequency, to signals applied at the input thereof; a third digital circuit which implements a counter function, and which comprises connections including at least a first input having functionality analogous to a conventional counter's reset input, and a second input having functionality analogous to a conventional counter's clock input, and a count output which is determined in accordance with said clock and reset inputs; wherein the output of said first digital circuit is connected to drive said first input of said third circuit, and the output of said second digital circuit is connected to drive said second input of said third circuit; whereby said count output of said third digital circuit provides said bandpass filter function.

Claim 4

An integrated circuit bandpass filter, for providing a passband with predetermined upper and lower passband edge frequencies, comprising: a first digital circuit which has an input and an output, said output responding with loss-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the lower passband edge frequency, to signals applied at the input thereof; a second digital circuit which has an input and an output, said output responding with low-pass frequency-domain response characteristics, which include a sharp cutoff at approximately the upper passband edge frequency, to signals applied at the input thereof; a third digital circuit which implements a counter function, and which comprises connections including at least a first input having functionality analogous to a conventional counter's reset input, and a second input having functionality analogous to a conventional counter's clock input, and a count output which is determined in accordance with said clock and reset inputs; wherein the output of said first digital circuit is connected to drive said first input of said third circuit, and the output of said second digital circuit is connected to drive said second input of said third circuit; whereby said count output of said third digital circuit provides said bandpass filter function.

Claim 5

The integrated circuit of claim 1, wherein said digital circuit is a counter.

Claim 6

The integrated circuit of claim 2, wherein said third digital circuit is a counter.

Claim 7

The integrated circuit of claim 1, wherein said first logic gate is an inverter.

Claim 8

The integrated circuit of claim 1, wherein said first logic gate is a NAND gate.

Claim 9

The integrated circuit of claim 1, wherein said first logic gate has two respective ones of said inputs.

Claim 10

The integrated circuit of claim 1, wherein exactly one of said first and second logic gates has two respective ones of said inputs.

Claim 11

The integrated circuit of claim 1, wherein at least one of said first and second logic gates has at least two respective ones of said inputs, and one of said inputs of both said logic gates is operatively connected to receive an input signal, and the output of said digital circuit is connected to provide a filtered output signal corresponding to said input signal.

Claim 12

The integrated circuit of claim 2, wherein said first digital circuit is an inverter.

Claim 13

The integrated circuit of claim 2, wherein said second digital circuit is an inverter.

Claim 14

The integrated circuit of claim 2, wherein said first and second digital circuits are inverters, and wherein said first digital circuit comprises a capacitor connected in parallel with the output of said first digital circuit.

Claim 15

The integrated circuit of claim 2, wherein said first and second digital circuits are inverters, and wherein said first digital circuit comprises a resistor connected in series with the output of said first digital circuit.

Claim 16

The integrated circuit of claim 1, wherein said first and second logic gates each comprise a resistor connected in series with the input thereof.

Claim 17

The integrated circuit of claim 2, wherein said first and second digital circuits are inverters, and wherein the input of said first digital circuit has a longer RC time constant than does the input to said second digital circuit.