US4241311A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital majority noise filter for bi-level data reception
Assignee: Telex Computer Products Inc
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Filing: 1979-02-01
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Granted: 1980-12-23
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Expires: 1999-02-01
Abstract
Abstract Apparatus for filtering high frequency noise pulses from alternating analog data of a frequency F, which includes means to convert the analog signal to a square wave bi-level signal, sampling the square wave signal at a clock frequency of at least 8F, loading the sampled signals into a digital shift register at the clock rate, reading out in parallel at least the last three samples, and passing said samples to a majority gate, which outputs a signal representing the majority polarity of the three signals read. The output of the majority gate is then applied to a latch in synchronism with the clock signal, which converts it back to a square wave signal representing the noise filtered version of the input signal.
Inventors
- 👤 Raymond P. Massey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:18
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
130 words
The method of filtering high frequency noise pulses from alternating analog data, of a selected frequency F, comprising the steps of: (a) forming a bi-level or square wave signal from said analog data; (b) providing a clock signal of a frequency of at least 8F; (c) sampling said bi-level data at the frequency of said clock signal, and reading said sampled data at clock frequency into a digital shift register; (d) reading out in parallel from said shift register a selected number of sampled bits, and into a majority gate in selected polarity; (e) applying the majority signal from said majority gate to a latch in synchronism with said clock signal, whereby the output of said latch will be the digital majority noise filtered version of the input analog signal.
Claim 2
Independent Claim
130 words
The method of filtering high frequency noise pulses from alternating analog data, of a selected frequency F, comprising the steps of: (a) forming a bi-level or square wave signal from said analog data; (b) providing a clock signal of a frequency of at least 8F; (c) sampling said bi-level data at the frequency of said clock signal, and reading said sampled data at clock frequency into a digital shift register; (d) reading out in parallel from said shift register a selected number of sampled bits, and into a majority gate in selected polarity; (e) applying the majority signal from said majority gate to a latch in synchronism with said clock signal, whereby the output of said latch will be the digital majority noise filtered version of the input analog signal.
Claim 3
Dependent Claim
29 words
The method as in claim 1 including the additional step of detecting the output signal of said latch at a selected time in the cycle of said bi-level signal.
Claim 4
Dependent Claim
35 words
The method as in claim 1 in which said clock frequency is 8F and the majority gate reads at least three adjacent digital bits and outputs the polarity of 2 out of 3 sequential bits.
Claim 5
Dependent Claim
32 words
The apparatus as in claim 2 in which said selected time in the cycle is in the vicinity of 1/2 cycle after the start of the positive half of said bi-level signal.
Claim 6
Dependent Claim
24 words
The apparatus as in claim 1 in which said clock frequency is 12F and the majority gate reads at least 3 adjacent digital bits.
Claim 7
Dependent Claim
24 words
The apparatus as in claim 1 in which said clock frequency is 12F and the majority gate reads at least 5 adjacent digital bits.
Claim 8
Dependent Claim
17 words
The method as in claim 1 in which the selected polarity of the sampled bits is positive.
Claim 9
Dependent Claim
17 words
The method as in claim 1 in which the selected polarity of the sampled bits is negative.
Claim 10
Dependent Claim
129 words
Apparatus for filtering high frequency noise pulses from alternating analog data of a selected frequency F, comprising; (a) receiver means to convert said analog input data to a bi-level or square wave signal; (b) clock means to provide a clock signal of a frequency of at least 8F; (c) means to sample said bi-level or square wave signal at the times of said clock signal, and to apply the stream of sampled signal bits to a digital shift register at the rate of said clock signal; (d) majority gate means, and means to apply a selected number of sampled bits loaded into said shift register to said majority gate; and (e) means to apply the output of said majority gate to a latch in synchronism with said clock signal.
Claim 11
Dependent Claim
129 words
Apparatus for filtering high frequency noise pulses from alternating analog data of a selected frequency F, comprising; (a) receiver means to convert said analog input data to a bi-level or square wave signal; (b) clock means to provide a clock signal of a frequency of at least 8F; (c) means to sample said bi-level or square wave signal at the times of said clock signal, and to apply the stream of sampled signal bits to a digital shift register at the rate of said clock signal; (d) majority gate means, and means to apply a selected number of sampled bits loaded into said shift register to said majority gate; and (e) means to apply the output of said majority gate to a latch in synchronism with said clock signal.
Claim 12
Dependent Claim
16 words
The apparatus as in claim 9 including means to utilize the output signal from said latch.
Claim 13
Dependent Claim
25 words
The apparatus as in claim 9 including means to detect the output latch signal at a selected time in the cycle of said bi-level signal.
Claim 14
Dependent Claim
32 words
The apparatus as in claim 11 in which said selected time in the cycle is in the vicinity of 1/2 cycle after the start of the positive half of said bi-level signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-23 | 1984-06-23 | 1984-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-23 | 1988-06-23 | 1988-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-23 | 1992-06-23 | 1992-12-23 | $7700.00 | Window Closed / Lapsed |