Semiconductor memory device having test mode

Claim 2

A semiconductor memory device comprising: a memory cell array, internal circuit means associated with data reading from said memory cell array and data writing to the same, reset pulse generating means responsive to a power supply for initializing said internal circuit means, said internal circuit means operating in response to an external control signal after the output of said reset pulse from said reset pulse generating means, test mode designating signal generating means responsive to said external control signal for generating a test mode designating signal designating a test mode, a first buffering means for buffering said external control signal and applying the same to said internal circuit means only when said reset pulse is not generated from said reset pulse generating means, and second buffering means for buffering said external control signal at all times and applying the same to said test mode designating signal generating means.

Claim 3

The semiconductor memory device according to claim 1, wherein said external control signal includes first, second and third signals, and said test mode designating signal generating means generates said test mode designating signal in response to a combination of the logical levels of the potentials of said first, second and third signals.

Claim 4

The semiconductor memory device according to claim 2, wherein when said first and second signals are at the first logical level, said test mode designating signal generating means generates said test mode designating signal in response to a change in the logical level of said third signal from said first logical level to a second logical level.

Claim 5

The semiconductor memory device according to claim 3, wherein said second buffering means includes first inverting means for inverting said third external control signal and second inverting means inverting the output of said first inverting means.

Claim 6

The semiconductor memory device according to claim 4, wherein said second buffering means further includes threshold voltage deviating means for deviating the threshold voltage of said second inverting means.

Claim 7

The semiconductor memory device according to claim 5, wherein said threshold voltage deviating means is provided between said first inverting means and said second inverting means and reduces a first threshold voltage corresponding to a switching of the output logical level of said second inverting means from said first logical level to said second logical level.

Claim 8

The semiconductor memory device according to claim 6, wherein said threshold voltage deviating means further increases a second threshold voltage corresponding to a switching of the output logical level of said second inverting means from said second logical level to said first logical level.

Claim 9

The semiconductor memory device according to claim 6, wherein said threshold voltage deviating means includes: switching means provided between the output of said first inverting means and a low potential source and controlled by the output of said second inverting means.

Claim 10

The semiconductor memory device according to claim 7, wherein said threshold voltage deviating means includes: first switching means provided between the output of said first inverting means and a high potential source and controlled by the output of said second inverting means, and second switching means provided between the output of said first inverting means and a low potential source and controlled by the output of said second inverting means.

Claim 11

The semiconductor memory device according to claim 8, wherein said switching means includes a field effect semiconductor element having a first conduction terminal receiving the output of said first inverting means, a second conduction terminal connected to said low potential source and a control terminal receiving the output of said second inverting means.

Claim 12

The semiconductor memory device according to claim 9, wherein said first switching means includes a first field effect semiconductor element of a first polarity having a first conduction terminal receiving the output of said first inverting means, a second conduction terminal connected to said high potential source and a control terminal receiving the output of said second inverting means, and said second switching means includes a second field effect semiconductor element of a second polarity opposite to said first polarity having a first conduction terminal receiving the output of said first inverting means, a second conduction terminal connected to said low potential source and a control terminal receiving the output of said second inverting means.

Claim 13

The semiconductor memory device according to claim 4, wherein said first buffering means includes: third inverting means inverting said third external control signal, fourth inverting means inverting the output of said third inverting means, and forcing means responsive to said reset pulse for temporarily forcing the output of said third inverting means to a predetermined potential.

Claim 14

The semiconductor memory device according to claim 5, wherein said first buffering means includes: third inverting means inverting said third external control signal, fourth inverting means inverting the output of said third inverting means, and forcing means responsive to said reset pulse for temporarily forcing the output of said third inverting means to a predetermined potential.

Claim 15

The semiconductor memory device according to claim 10, wherein said first inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by said third external control signal, and said second inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by the potential at a node between said two field effect semiconductor elements.

Claim 16

The semiconductor memory device according to claim 11, wherein said first inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by said third external control signal, and said second inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by the potential at a node between said two field effect semiconductor elements.

Claim 17

The semiconductor memory device according to claim 12, wherein said third inverting means includes two field effect semiconductor elements connected in series between a high potential source and a low potential source, having polarities complementary to each other and controlled by said third external control signal, said fourth inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by the potential at a node between said two field effect semiconductor elements, and said forcing means includes a field effect semiconductor element connected in parallel to one of said two field effect semiconductor elements included in said third inverting means, responsive to said reset pulse for conducting and having the same polarity as that of said one element, and a field effect semiconductor element connected in series to the other element of said two field effect semiconductor elements included in said third inverting means, responsive to said reset pulse for entering a non-conductive state and having the same polarity as that of said the other element.

Claim 18

The semiconductor memory device according to claim 13, wherein said third inverting means includes two field effect semiconductor elements connected in series between a high potential source and a low potential source, having polarities complementary to each other and controlled by said third external control signal, said fourth inverting means includes two field effect semiconductor elements connected in series between said high potential source and said low potential source, having polarities complementary to each other and controlled by the potential at a node between said two field effect semiconductor elements, and said forcing means includes a field effect semiconductor element connected in parallel to one of said two field effect semiconductor elements included in said third inverting means, responsive to said reset pulse for conducting and having the same polarity as that of said one element, and a field effect semiconductor element connected in series to the other element of said two field effect semiconductor elements included in said third inverting means, responsive to said reset pulse for entering a non-conductive state and having the same polarity as that of said the other element.

Claim 19

The semiconductor memory device according to claim 6, wherein the difference between said first threshold voltage and said second threshold voltage V3 corresponding to a switching of the output level of said second inverting means from said second logical level to said first logical level is larger than the potential fluctuation amount of said third external control signal due to noise immediately after said power supply.

Claim 20

The semiconductor memory device according to claim 7, wherein the difference between said first threshold voltage and said second threshold voltage is larger than the potential fluctuation amount of said third external control signal due to noise immediately after said power supply.

Claim 21

A semiconductor memory device comprising: a memory cell array; control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal, said control means comprising a first buffer means for buffering said external signal and reset means responsive to a power supply for initializing said first buffer means; test mode designating means for controlling initiation and termination of a test operation of said memory cell array in response to said external control signal; and a second buffer means for buffering said external control signal, said test mode designating means connected to an output of said second buffer means.

Claim 22

A semiconductor memory device comprising: a memory cell array; control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal, said control means comprising a first buffer means for buffering said external signal and reset means responsive to a power supply for initializing said first buffer means; test mode designating means for controlling initiation and termination of a test operation of said memory cell array in response to said external control signal; and a second buffer means for buffering said external control signal, said test mode designating means connected to an output of said second buffer means.

Claim 23

The semiconductor memory device according to claim 20 wherein said second buffer means comprises a first inverting means for inverting said external control signal and a second inverting means for inverting an output of said first inverting means and an output of said second inverting means is connected to said test mode designating means.

Claim 24

The semiconductor memory device according to claim 21, wherein said second buffer means further includes threshold voltage setting means for setting a threshold voltage of said second inverting means at a first level for an increased change in voltage input to said second inverting means and at a second level for a decreased change in voltage input to said second inverting means.

Claim 25

The semiconductor memory device according to claim 22, wherein said first level is higher than said second level.

Claim 26

A semiconductor memory device capable of performing normal mode and test mode operation, comprising: a memory cell array; control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal; test mode designating means for setting and resetting test mode operation of said memory cell array in response to said control means; said control means comprising a first buffer means comprising a plurality of inverters for buffering said external signal and a second buffer means comprising a plurality of inverters for buffering said external control signal, said second buffer means having a higher hysteresis voltage threshold level than said first buffer means; and said test mode designating means connected to an output of said second buffer means.

Claim 27

A semiconductor memory device capable of performing normal mode and test mode operation, comprising: a memory cell array; control means for controlling normal reading and writing operations of said memory cell array in response to an external control signal; test mode designating means for setting and resetting test mode operation of said memory cell array in response to said control means; said control means comprising a first buffer means comprising a plurality of inverters for buffering said external signal and a second buffer means comprising a plurality of inverters for buffering said external control signal, said second buffer means having a higher hysteresis voltage threshold level than said first buffer means; and said test mode designating means connected to an output of said second buffer means.

Claim 28

The semiconductor memory device according to claim 24, wherein said external control signal includes first, second and third signals, and said test mode designating means generates a test mode designating signal in response to a combination of the logical levels of the potentials of said first, second and third signals.

Claim 29

The semiconductor memory device according to claim 25, wherein when said first and second signals are at the first logical level, said test mode designating means generates said test mode designating signal in response to a change in the logical level of said third signal from said first logical level to a second logical level.

Claim 30

The semiconductor memory device according to claim 25, wherein said second buffering means includes first inverting means for inverting said third external control signal and second inverting means inverting the output of said first inverting means.

Claim 31

The semiconductor memory device according to claim 27, wherein said second buffering means further includes threshold voltage deviating means for deviating the threshold voltage of said second inverting means.

Claim 32

The semiconductor memory device according to claim 28, wherein said threshold voltage deviating means is provided between said first inverting means and said second inverting means and reduces a first threshold voltage corresponding to a switching of the output logical level of said second inverting means from said first logical level to said second logical level.

Claim 33

The semiconductor memory device according to claim 29, wherein said threshold voltage deviating means further increases a second threshold voltage corresponding to a switching of the output logical level of said second inverting means from said second logical level to said first logical level.

Claim 34

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first internal address strobe signal to said row decoder in response to an external row address strobe signal and a voltage level of a power on reset signal; and a second input buffer means formed on said substrate for generating a second internal row address strobe signal in response to said external row address strobe signal; and means for applying said second internal row address strobe signal to said test mode control means.

Claim 35

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first internal address strobe signal to said row decoder in response to an external row address strobe signal and a voltage level of a power on reset signal; and a second input buffer means formed on said substrate for generating a second internal row address strobe signal in response to said external row address strobe signal; and means for applying said second internal row address strobe signal to said test mode control means.

Claim 36

The semiconductor memory device according to claim 31, wherein said second input buffer means includes first inverting means for inverting said external address strobe signal and second inverting means inverting the output of said first inverting means.

Claim 37

The semiconductor memory device according to claim 32, wherein said second input buffer means further includes threshold voltage deviating means for deviating the threshold voltage of said second inverting means.

Claim 38

The semiconductor memory device according to claim 33, wherein said threshold voltage deviating means is provided between said first inverting means and said second inverting means and reduces a first threshold voltage corresponding to a switching of the output logical level of said second inverting means from said first logical level to said second logical level.

Claim 39

The semiconductor memory device according to claim 34, wherein said threshold voltage deviating means further increases a second threshold voltage corresponding to a switching of the output logical level of said second inverting means from said second logical level to said first logical level.

Claim 40

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second bilevel internal row address strobe signal changing between a first level and a second level on a delayed basis in comparison with said first internal address strobe signal.

Claim 41

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second bilevel internal row address strobe signal changing between a first level and a second level on a delayed basis in comparison with said first internal address strobe signal.

Claim 42

The semiconductor memory device according to claim 36, wherein said second input buffer means includes first inverting means for inverting said external address strobe signal and second inverting means inverting the output of said first inverting means.

Claim 43

The semiconductor memory device according to claim 37, wherein said second input buffer means further includes threshold voltage deviating means for deviating the threshold voltage of said second inverting means.

Claim 44

The semiconductor memory device according to claim 38, wherein said threshold voltage deviating means is provided between said first inverting means and said second inverting means and reduces a first threshold voltage corresponding to a switching of the output logical level of said second inverting means from said first logical level to said second logical level.

Claim 45

The semiconductor memory device according to claim 39, wherein said threshold voltage deviating means further increases a second threshold voltage corresponding to a switching of the output logical level of said second inverting means from said second logical level to said first logical level.

Claim 46

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, a threshold voltage required for changing from a low level to a high level in said second input buffer means being higher than a threshold voltage required for changing from a low level to a high level in said first input buffer.

Claim 47

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, a threshold voltage required for changing from a low level to a high level in said second input buffer means being higher than a threshold voltage required for changing from a low level to a high level in said first input buffer.

Claim 48

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second input buffer means having a predetermined voltage difference between a threshold voltage required for changing said second bilevel internal row address strobe signal from a low level to a high level and a threshold voltage required for changing said second bilevel internal row address strobe signal from a high level to a low level.

Claim 49

A semiconductor memory device comprising: a memory cell array formed on a semiconductor substrate and comprising a plurality of memory cells arranged in rows and columns; a plurality of word lines formed on said substrate and corresponding to said rows of memory cells; a row decoder formed on said substrate for decoding an applied address signal corresponding to a selected word line; a test mode control means formed on said substrate for generating a test mode signal for setting said device to test mode operation; a first input buffer means formed on said substrate for applying a first bilevel internal address strobe signal to said row decoder in response to an external bilevel row address strobe signal; and a second input buffer means formed on said substrate for generating a second bilevel internal row address strobe signal in response to said external row address strobe signal, said second input buffer means having a predetermined voltage difference between a threshold voltage required for changing said second bilevel internal row address strobe signal from a low level to a high level and a threshold voltage required for changing said second bilevel internal row address strobe signal from a high level to a low level.

Claim 50

A semiconductor memory device comprising: a memory cell array, internal circuit means associated with data from said memory cell array and data writing to the same, reset pulse generating means responsive to a power supply for generating a reset pulse initializing said internal circuit means, said internal circuit means operating in response to first, second and third external control signals after said reset pulse is output from said reset pulse generating means, test mode designating signal generating means responsive to a change in the logical level of said third external control signal from a first logical level to a second logical level when said first and second external control signals are at a predetermined logical level for generating a test mode designating signal designating a test mode, first external control signal buffering means for buffering said first external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means, second external control signal buffering means for buffering said second external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means, first means for buffering said third external control signal for buffering said third external control signal only when said reset pulse is not generated from said reset pulse generating means and applying the same to said internal circuit means, and second means for buffering said third external control signal for buffering said third external control signal at all times without being controlled by said reset pulse and applying the same to said test mode designating signal generating means.

Claim 51

A semiconductor memory device comprising: a memory cell array, internal circuit means associated with data from said memory cell array and data writing to the same, reset pulse generating means responsive to a power supply for generating a reset pulse initializing said internal circuit means, said internal circuit means operating in response to first, second and third external control signals after said reset pulse is output from said reset pulse generating means, test mode designating signal generating means responsive to a change in the logical level of said third external control signal from a first logical level to a second logical level when said first and second external control signals are at a predetermined logical level for generating a test mode designating signal designating a test mode, first external control signal buffering means for buffering said first external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means, second external control signal buffering means for buffering said second external control signal at all times without being controlled by said reset pulse and applying the same to said internal circuit means and said test mode designating signal generating means, first means for buffering said third external control signal for buffering said third external control signal only when said reset pulse is not generated from said reset pulse generating means and applying the same to said internal circuit means, and second means for buffering said third external control signal for buffering said third external control signal at all times without being controlled by said reset pulse and applying the same to said test mode designating signal generating means.