US5073874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of and apparatus for reducing current of semiconductor memory device
Assignee: Mitsubishi Electric Corp
•
Filing: 1989-10-04
•
Granted: 1991-12-17
•
Expires: 2009-10-04
Abstract
Abstract A clock generator circuit of a dynamic RAM comprises a power-on reset circuit and an NOR gate connected to a RAS terminal and the reset circuit. In operation, the powre-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level RAS signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic RAM at the time of turning on the power supply.
Inventors
- 👤 Michihiro Yamada
- 👤 Hiroshi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076
Claims Analysis
Total Claims: 65
Claim 1
Independent Claim
234 words
A semiconductor memory device operative in a first operating state and a second operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device consumes more current in said first operating state than in said second operating state, reading and writing operations of said memory device being inhibited in said second operating state, said semiconductor memory device comprising: at least one memory cell for storing data first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector mans for detecting an application of power to said memory device; generating means responsive to said detector means for generating a power-on reset pulse signal defining said second operating state of said memory device for a predetermined time period initiated upon said detector means detecting application of power to said memory device; and second control means responsive to the external control signal and to said power-on reset pulse signal for selectively operating said memory device in said first and second operating states whereby said memory device is operated in said second operating state both in response to application of power thereto and in response to said external control signal to reduce an initial current requirement of said memory upon initial power application thereto.
Claim 2
Dependent Claim
234 words
A semiconductor memory device operative in a first operating state and a second operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device consumes more current in said first operating state than in said second operating state, reading and writing operations of said memory device being inhibited in said second operating state, said semiconductor memory device comprising: at least one memory cell for storing data first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector mans for detecting an application of power to said memory device; generating means responsive to said detector means for generating a power-on reset pulse signal defining said second operating state of said memory device for a predetermined time period initiated upon said detector means detecting application of power to said memory device; and second control means responsive to the external control signal and to said power-on reset pulse signal for selectively operating said memory device in said first and second operating states whereby said memory device is operated in said second operating state both in response to application of power thereto and in response to said external control signal to reduce an initial current requirement of said memory upon initial power application thereto.
Claim 3
Dependent Claim
19 words
A semiconductor memory device according to claim 1, wherein said first and second control means comprise one control means.
Claim 4
Dependent Claim
39 words
A semiconductor memory device according to claim 2, wherein said second control means comprises a NOR device means having at least two inputs, with said two inputs connected to receive the external control signal and the power-on reset signal.
Claim 5
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein said external control signal comprises at least one of a row address strobe signal and a column address strobe signal.
Claim 6
Dependent Claim
24 words
A semiconductor memory device according to claim 1, wherein a pulse width of said power-on reset pulse is equal to said predetermined time period.
Claim 7
Dependent Claim
31 words
A semiconductor memory device according to claim 1 wherein said generating means includes means for controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 8
Dependent Claim
59 words
A semiconductor memory device according to claim 1 wherein said generating means includes timing means for controlling a duration of said power-on reset pulse to be equal to said predetermined time period, said timing means including a combination of a load device and a capacitor a charging time constant characteristic of which is used to control said pulse duration.
Claim 9
Dependent Claim
36 words
A semiconductor memory device according to claim 7 wherein a time constant of said combination of said load device and said capacitor is greater than a rise time of said power applied to said memory device.
Claim 10
Dependent Claim
18 words
A semiconductor memory device according to claim 7 wherein said load device comprises a field effect transistor (FET).
Claim 11
Dependent Claim
30 words
A semiconductor memory device according to claim 7 wherein said load device comprises a field effect transistor (FET) connected in series with said capacitor between first and second voltage potentials.
Claim 12
Dependent Claim
34 words
A semiconductor memory device according to claim 1 further comprising a semiconductor substrate wherein said memory cell, said generating means and said first and second control means are all formed on said semiconductor substrate.
Claim 13
Dependent Claim
239 words
A dynamic random access memory device (DRAM) operative in a first operating state and a second operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device consumes more current in said first operating state than in said second operating state, reading and writing operations of said memory device being inhibited in said second operating state, said dynamic random access memory device comprising: at least one memory cell for storing data; first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector means for detecting an application of power to said memory device; generating means responsive to said detector means for generating a power-on reset pulse signal defining said second operating state of said memory device for a predetermined time period initiated upon said detector means detecting application of power to said memory device; and second control means responsive to the external control signal and to said power-on reset pulse signal for selectively operating said memory device in said first and second operating states whereby said memory device is operated in said second operating state both in response to application of power thereto and in response to said external control signal to reduce an initial current requirement of said memory upon initial power application thereto.
Claim 14
Dependent Claim
239 words
A dynamic random access memory device (DRAM) operative in a first operating state and a second operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device consumes more current in said first operating state than in said second operating state, reading and writing operations of said memory device being inhibited in said second operating state, said dynamic random access memory device comprising: at least one memory cell for storing data; first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states; detector means for detecting an application of power to said memory device; generating means responsive to said detector means for generating a power-on reset pulse signal defining said second operating state of said memory device for a predetermined time period initiated upon said detector means detecting application of power to said memory device; and second control means responsive to the external control signal and to said power-on reset pulse signal for selectively operating said memory device in said first and second operating states whereby said memory device is operated in said second operating state both in response to application of power thereto and in response to said external control signal to reduce an initial current requirement of said memory upon initial power application thereto.
Claim 15
Dependent Claim
30 words
A dynamic random access memory device according to claim 12, wherein said first operating state comprises an active operating state, and said second operating state comprises a standby operating state.
Claim 16
Dependent Claim
32 words
A dynamic random access memory device according to claim 13, wherein said memory device has a tendency to be in said active operating state when power is applied for a first time.
Claim 17
Dependent Claim
26 words
A dynamic random access memory device according to claim 12 wherein a pulse width of said power-on reset pulse is equal to said predetermined time period.
Claim 18
Dependent Claim
33 words
A dynamic random access memory device according to claim 12 wherein said generating means includes means for controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 19
Dependent Claim
61 words
A dynamic random access memory device according to claim 12 wherein said generating means includes timing means for controlling a duration of said power-on reset pulse to be equal to said predetermined time period, said timing means including a combination of a load device and a capacitor a charging time constant characteristic of which is used to control said pulse duration.
Claim 20
Dependent Claim
38 words
A dynamic random access memory device according to claim 17 wherein a time constant of said combination of said load device and said capacitor is greater than a rise time of said power applied to said memory device.
Claim 21
Dependent Claim
20 words
A dynamic random access memory device according to claim 17 wherein said load device comprises a field effect transistor (FET).
Claim 22
Dependent Claim
32 words
A dynamic random access memory device according to claim 17 wherein said load device comprises a field effect transistor (FET) connected in series with said capacitor between first and second voltage potentials.
Claim 23
Dependent Claim
36 words
A dynamic random access memory device according to claim 12 further comprising a semiconductor substrate wherein said memory cell, said generating means and said first and second control means are all formed on said semiconductor substrate.
Claim 24
Independent Claim
190 words
A method for operating a semiconductor memory device operative in a first operating state and a second operating state to reduce an initial current requirement of said memory upon initial power application thereto, wherein said device consumes more current in said first operating state than in said second operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, reading and writing operations of said memory device being inhibited in said second operating state, said semiconductor device comprising at least one memory cell for storing data; and first control means responsive to an external signal for controlling said memory device to operate selectively in said first and second operating states, said method comprising the steps of: detecting an application of power to said memory device; generating a power-on reset pulse signal defining said second operating state of said memory device in response to the application of power to said memory device; and automatically operating said memory device in said second operating state for a predetermined time period responsive to said power-on reset pulse signal.
Claim 25
Independent Claim
190 words
A method for operating a semiconductor memory device operative in a first operating state and a second operating state to reduce an initial current requirement of said memory upon initial power application thereto, wherein said device consumes more current in said first operating state than in said second operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, reading and writing operations of said memory device being inhibited in said second operating state, said semiconductor device comprising at least one memory cell for storing data; and first control means responsive to an external signal for controlling said memory device to operate selectively in said first and second operating states, said method comprising the steps of: detecting an application of power to said memory device; generating a power-on reset pulse signal defining said second operating state of said memory device in response to the application of power to said memory device; and automatically operating said memory device in said second operating state for a predetermined time period responsive to said power-on reset pulse signal.
Claim 26
Dependent Claim
32 words
A method of operating a semiconductor memory device according to claim 22 wherein said power-on reset pulse generated by said generating step has a pulse width equal to said predetermined time period.
Claim 27
Dependent Claim
36 words
A method of operating a semiconductor memory device according to claim 22 wherein said generating step includes a step of controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 28
Dependent Claim
53 words
A method of operating a semiconductor memory device according to claim 22 wherein said generating step includes the steps of charging a capacitor through a load device, detecting a predetermined voltage of said capacitor, and, in response, controlling a duration of said power-on reset pulse to be equal to said predetermine time period.
Claim 29
Dependent Claim
45 words
A method of operating a semiconductor memory device according to claim 25 including a step of selecting a time constant of said combination of said load device and said capacitor to be greater than a rise time of said power applied to said memory device.
Claim 30
Independent Claim
197 words
A method for operating a dynamic random access memory device (CRAM) operative in a first operating state and a second operating state to reduce an initial current requirement of said memory upon initial power application thereto, wherein said device consumes more current in said first operating state than in said second operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, reading and writing operations of said memory device being inhibited in said second operating state, said dynamic random access memory device comprising at least one memory cell for storing data; and first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states, said method comprising the steps of: detecting an application of power to said memory device; generating a power-on reset pulse signal defining said second operating state of said memory device in response to the application of power to said memory device; and automatically operating said memory device in said second operating state for a predetermined time period responsive to said power-on reset pulse signal.
Claim 31
Independent Claim
197 words
A method for operating a dynamic random access memory device (CRAM) operative in a first operating state and a second operating state to reduce an initial current requirement of said memory upon initial power application thereto, wherein said device consumes more current in said first operating state than in said second operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, reading and writing operations of said memory device being inhibited in said second operating state, said dynamic random access memory device comprising at least one memory cell for storing data; and first control means responsive to an external control signal for controlling said memory device to operate selectively in said first and second operating states, said method comprising the steps of: detecting an application of power to said memory device; generating a power-on reset pulse signal defining said second operating state of said memory device in response to the application of power to said memory device; and automatically operating said memory device in said second operating state for a predetermined time period responsive to said power-on reset pulse signal.
Claim 32
Dependent Claim
34 words
A method of operating a dynamic random access memory device according to claim 27 wherein said power-on reset pulse generated by said generating step has a pulse width equal to said predetermined time period.
Claim 33
Dependent Claim
38 words
A method of operating a dynamic random access memory device according to claim 27 wherein said generating step includes a step of controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 34
Dependent Claim
55 words
A method of operating a dynamic random access memory device according to claim 27 wherein said generating step includes the steps of charging a capacitor through a load device, detecting a predetermined voltage of said capacitor, and, in response, controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 35
Dependent Claim
47 words
A method of operating a dynamic random access memory device according to claim 30 including a step of selecting a time constant of said combination of said load device and said capacitor to be greater than a rise time of said power applied to said memory device.
Claim 36
Dependent Claim
201 words
A semiconductor memory device having a memory cell for storing data and receiving an external row address strobe signal, said semiconductor memory device requiring an initial surge current upon initial power application thereto that is higher than an steady-state operating current requirement of said semiconductor memory device, said semiconductor memory device comprising: a NOR logic circuit having first and second input terminals and an output terminal, said first input terminal receiving said external row address strobe signal, said second input terminal receiving a control signal, and said output terminal supplying an internal row address strobe signal for controlling access to said memory cell; and a signal generator circuit having a load device and a capacitor coupled in series with each other between a first potential source and a second potential source, and an inverter circuit having an input terminal coupled to a node between said load device and said capacitor and an output terminal providing said control signal to said second input terminal of said NOR logic circuit whereby an operation of said load device and said capacitor defines a time period defining a duration of said control signal to reduce the initial surge current requirement of said semiconductor memory device.
Claim 37
Dependent Claim
201 words
A semiconductor memory device having a memory cell for storing data and receiving an external row address strobe signal, said semiconductor memory device requiring an initial surge current upon initial power application thereto that is higher than an steady-state operating current requirement of said semiconductor memory device, said semiconductor memory device comprising: a NOR logic circuit having first and second input terminals and an output terminal, said first input terminal receiving said external row address strobe signal, said second input terminal receiving a control signal, and said output terminal supplying an internal row address strobe signal for controlling access to said memory cell; and a signal generator circuit having a load device and a capacitor coupled in series with each other between a first potential source and a second potential source, and an inverter circuit having an input terminal coupled to a node between said load device and said capacitor and an output terminal providing said control signal to said second input terminal of said NOR logic circuit whereby an operation of said load device and said capacitor defines a time period defining a duration of said control signal to reduce the initial surge current requirement of said semiconductor memory device.
Claim 38
Dependent Claim
17 words
A semiconductor memory device to claim 32 wherein said load means comprises a field effect transistor (FET).
Claim 39
Dependent Claim
35 words
A semiconductor memory device according to claim 32 wherein a time constant of said combination of said load device and said capacitor is greater than rise time of said power applied to said memory device.
Claim 40
Dependent Claim
176 words
A semiconductor memory device operative in an active operating state and a standby operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state, said semiconductor memory device comprising: generating means for generating a power-on reset pulse signal for controlling said memory device to operate in said standby operating state for a predetermined period of time whenever a predetermined power is applied to said memory device; and control means for (1) operating said memory device in said standby operating state for said predetermined period of time responsive to said power-on reset pulse signal and then (2) operating said memory device in one of said operating states responsive to said control signal to reduce the initial power supply requirement of said memory device.
Claim 41
Dependent Claim
176 words
A semiconductor memory device operative in an active operating state and a standby operating state and requiring an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state, said semiconductor memory device comprising: generating means for generating a power-on reset pulse signal for controlling said memory device to operate in said standby operating state for a predetermined period of time whenever a predetermined power is applied to said memory device; and control means for (1) operating said memory device in said standby operating state for said predetermined period of time responsive to said power-on reset pulse signal and then (2) operating said memory device in one of said operating states responsive to said control signal to reduce the initial power supply requirement of said memory device.
Claim 42
Dependent Claim
24 words
A semiconductor memory device according to claim 35 wherein a pulse width of said power-on reset pulse is equal to said predetermined time period.
Claim 43
Dependent Claim
31 words
A semiconductor memory device according to claim 35 wherein said generating means includes mean for controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 44
Dependent Claim
59 words
A semiconductor memory device according to claim 35 wherein said generating means includes timing means for controlling a duration of said power-on reset pulse to be equal to said predetermined time period, said timing means including a combination of a load device and a capacitor a charging time constant characteristic of which is used to control said pulse duration.
Claim 45
Dependent Claim
18 words
A semiconductor memory device according to claim 38 wherein said load device comprises a field effect transistor (FET).
Claim 46
Dependent Claim
30 words
A semiconductor memory device according to claim 38 wherein said load device comprises a field effect transistor (FET) connected in series with said capacitor between first and second voltage potentials.
Claim 47
Dependent Claim
36 words
A semiconductor memory device according to claim 38 wherein a time constant of said combination of said load device and said capacitor is greater than a rise time of said power applied to said memory device.
Claim 48
Dependent Claim
34 words
A semiconductor memory device according to claim 35 further comprising a semiconductor substrate wherein said memory cell, said generating means and said first and second control means are all formed on said semiconductor substrate.
Claim 49
Dependent Claim
34 words
A semiconductor memory device according to claim 35 wherein said predetermined time period is selected to suppress an initial current surge requirement of said semiconductor memory device upon said initial application of power thereto.
Claim 50
Independent Claim
202 words
A method for operating a semiconductor memory device operative in an active operating state and a standby operating state to reduce an initial power supply requirement of said memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, said method comprising the steps of: (a) detecting application of a predetermined power to said memory device; (b) generating a power-on reset pulse signal in response to step (a) for controlling said memory device to operate in said standby operating state for a predetermined period of time; and (c) operating said memory device in said standby operating state in response to said power-on reset pulse signal for said predetermined period of time and operating said memory device in one of said operating states responsive to said control signal subsequent to expiration of said predetermined period of time to reduce the initial power supply current requirement of said memory device.
Claim 51
Independent Claim
202 words
A method for operating a semiconductor memory device operative in an active operating state and a standby operating state to reduce an initial power supply requirement of said memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, said method comprising the steps of: (a) detecting application of a predetermined power to said memory device; (b) generating a power-on reset pulse signal in response to step (a) for controlling said memory device to operate in said standby operating state for a predetermined period of time; and (c) operating said memory device in said standby operating state in response to said power-on reset pulse signal for said predetermined period of time and operating said memory device in one of said operating states responsive to said control signal subsequent to expiration of said predetermined period of time to reduce the initial power supply current requirement of said memory device.
Claim 52
Dependent Claim
32 words
A method of operating a semiconductor memory device according to claim 44 wherein said power-on reset pulse generated by said generating step has a pulse width equal to said predetermined time period.
Claim 53
Dependent Claim
37 words
A method of operating a semiconductor memory device in according to claim 44 wherein said generating step includes a step of controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 54
Dependent Claim
53 words
A method of operating a semiconductor memory device according to claim 24 wherein said generating step includes the steps of charging a capacitor through a load device, detecting a predetermined voltage of said capacitor, and, in response, controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 55
Dependent Claim
45 words
A method of operating a semiconductor memory device according to claim 47 including a step of selecting a time constant of said combination of said load device and said capacitor to be greater than a rise time of said power applied to said memory device.
Claim 56
Independent Claim
180 words
A method for operating a semiconductor memory device operative in an active operating state and a standby operating state to reduce an initial power supply current requirement of said memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, said method comprising the steps of: (a) detecting application of a predetermined power to said memory device; (b) generating a power-on reset pulse signal in response to step (a) for controlling said memory device to operate in said standby operating state for a predetermined period of time; and (c) inhibiting operation of said memory device in said active operating state for said predetermined period of time in response to said power-on reset pulse signal to reduce the initial power supply current requirement of said memory device.
Claim 57
Independent Claim
180 words
A method for operating a semiconductor memory device operative in an active operating state and a standby operating state to reduce an initial power supply current requirement of said memory device, wherein said memory device receives a control signal for controlling said memory device to operate selectively in said active and standby operating states, reading and writing operations of said memory device being inhibited in said standby operating state and requires an initial surge current upon initial power application thereto that is higher than a steady-state operating current requirement of said semiconductor memory device, said method comprising the steps of: (a) detecting application of a predetermined power to said memory device; (b) generating a power-on reset pulse signal in response to step (a) for controlling said memory device to operate in said standby operating state for a predetermined period of time; and (c) inhibiting operation of said memory device in said active operating state for said predetermined period of time in response to said power-on reset pulse signal to reduce the initial power supply current requirement of said memory device.
Claim 58
Dependent Claim
32 words
A method of operating a semiconductor memory device according to claim 49 wherein said power-on reset pulse generated by said generating step has a pulse width equal to said predetermined time period.
Claim 59
Dependent Claim
37 words
A method of operating a semiconductor memory device in according to claim 49 wherein said generating step includes a step of controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 60
Dependent Claim
53 words
A method of operating a semiconductor memory device according to claim 49 wherein said generating step includes the steps of charging a capacitor through a load device, detecting a predetermined voltage of said capacitor, and, in response, controlling a duration of said power-on reset pulse to be equal to said predetermined time period.
Claim 61
Dependent Claim
45 words
A method of operating a semiconductor memory device according to claim 52 including a step of selecting a time constant of said combination of said load device and said capacitor to be greater than a rise time of said power applied to said memory device.
Claim 62
Dependent Claim
145 words
A semiconductor memory device having a plurality of memory cells, comprising: a semiconductor substrate; an internal circuit means including clock generating means, row and column addressing means and sense amplifying means; a control signal terminal receiving an external control signal and formed on said semiconductor substrate; a power supply terminal receiving a power supply and formed on said substrate; a power-on reset signal generating means formed on said semiconductor substrate and connected to said power supply terminal for generating a power-on reset pulse having a predetermined width when said power supply is applied to said power supply terminal; and a control means formed on said semiconductor substrate and connected to said control signal terminal and the output node of said generating means for supplying an internal control signal formed by combining said external control signal and power-on reset pulse for controlling said internal circuit means.
Claim 63
Dependent Claim
145 words
A semiconductor memory device having a plurality of memory cells, comprising: a semiconductor substrate; an internal circuit means including clock generating means, row and column addressing means and sense amplifying means; a control signal terminal receiving an external control signal and formed on said semiconductor substrate; a power supply terminal receiving a power supply and formed on said substrate; a power-on reset signal generating means formed on said semiconductor substrate and connected to said power supply terminal for generating a power-on reset pulse having a predetermined width when said power supply is applied to said power supply terminal; and a control means formed on said semiconductor substrate and connected to said control signal terminal and the output node of said generating means for supplying an internal control signal formed by combining said external control signal and power-on reset pulse for controlling said internal circuit means.
Claim 64
Dependent Claim
66 words
A semiconductor memory device according to claim 54, wherein said external control signal is an external Row Address Strobe signal, and said control means supplies an internal Row Address Strobe Signal formed by said external Row Address Signal, and selectively supplies (i) a predetermined potential during said power-on reset pulse and (ii) an internal Row Address Strobe in the absence of said power on reset pulse.
Claim 65
Dependent Claim
50 words
A semiconductor memory device according to claim 54, wherein said external control signal is a Row Address Strobe signal and said control means selectively supplies (i) a predetermined potential during said power-on reset pulse and (ii) an internal Row Address Strobe signal in the absence of said power-on reset pulse.
References Cited (Backward Citations)
US3562555A
Cited
US4174541A
Cited
US4216389A
Cited
US4398102A
Cited
US4451742A
Cited
US4409501A
Cited
US4422163A
Cited
US4578774A
Cited
US4654829A
Cited
US4712196A
Cited
US4777626A
Cited
US4788454A
Cited
US4864541A
Cited
US4849654A
Cited
US4886984A
Cited
US4900950A
Cited
US4874965A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |