Patent US5202967A successfully refreshed from Google Patents.
US5202967A
Expired / Lapsed
US
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Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
Assignee: Panasonic Holdings Corp
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Filing: 1992-07-20
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Granted: 1993-04-13
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Expires: 2012-07-20
Abstract
Abstract A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.
Inventors
- 👤 Toshimichi Matsuzaki
- 👤 Takashi Sakao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/30145; G06F9/30149; G06F9/3818; G06F9/3822; G06F9/3836; G06F9/3842
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
238 words
A data processing apparatus for decoding in parallel a plurality of instructions of a variable word length instruction system including at least one fixed length instruction, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; and said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder means and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means.
Claim 2
Dependent Claim
238 words
A data processing apparatus for decoding in parallel a plurality of instructions of a variable word length instruction system including at least one fixed length instruction, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; and said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder means and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means.
Claim 3
Dependent Claim
324 words
A data processing apparatus for processing in parallel a conditional branch instruction and subsequent instructions including conditional branch instructions, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; and said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means; an adder receiving an instruction from said second instruction decoder when said parallel-decodable instruction is a conditional branch instruction and for calculating and outputting a branch target address of said conditional branch instruction; a comparator for detecting whether conditions defined in the conditional branch instruction are met; and branch control means for suppressing an execution of instructions subsequent to the conditional branch instruction only in response to an indication by said comparator that the conditions are met and for starting an execution of the instruction from the branch target address outputted by the adder.
Claim 4
Dependent Claim
324 words
A data processing apparatus for processing in parallel a conditional branch instruction and subsequent instructions including conditional branch instructions, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; and said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means; an adder receiving an instruction from said second instruction decoder when said parallel-decodable instruction is a conditional branch instruction and for calculating and outputting a branch target address of said conditional branch instruction; a comparator for detecting whether conditions defined in the conditional branch instruction are met; and branch control means for suppressing an execution of instructions subsequent to the conditional branch instruction only in response to an indication by said comparator that the conditions are met and for starting an execution of the instruction from the branch target address outputted by the adder.
Claim 5
Dependent Claim
347 words
A data processing apparatus, for use with a memory unit, for processing in parallel a data transmission instruction between said memory unit and an internal register and its subsequent instructions, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder means and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means; reading means for receiving an instruction from said second instruction decoder means when said parallel-decodable instruction is a data transmission instruction and for reading data from the memory unit according to the data transmission instruction; operating means for performing an operation to be completed by using a plurality of registers according to the subsequent instructions; delay control means for delay operation of the operating means until necessary data for the operation are obtained in response to instructions decoded by the first instruction decoder means and the second instruction decoder means; and writing means for writing data into the memory unit according to the data transmission instruction.
Claim 6
Dependent Claim
347 words
A data processing apparatus, for use with a memory unit, for processing in parallel a data transmission instruction between said memory unit and an internal register and its subsequent instructions, comprising: instruction supplying means for providing a first instruction having a variable word length and a second instruction subsequent to said first instruction; a first instruction decoder means for receiving and decoding said first instruction and providing a signal indicative of a boundary of the first instruction; parallel decoding probability detection means for receiving said second instruction while the first instruction is currently being decoded by the first instruction decoder means, for decoding said second instruction and for detecting whether the second instruction is a parallel-decodable instruction which has a fixed length and is decodable in parallel with an instruction decoded in said first instruction decoder means; at least one second instruction decoder means for decoding the parallel-decodable instruction detected as parallel-decodable by the parallel decoding probability detection means in parallel with an instruction decoded in said first instruction decoder; said instruction supplying means for selectively validating the parallel-decodable instruction detected by the parallel decoding probability detection means as a validated parallel-decodable instruction in accordance with the signal indicative of the boundary of the first instruction outputted by the first instruction decoder means, and for supplying the validated parallel-decodable instruction to the second instruction decoder means and an instruction subsequent to the validated parallel-decodable instruction to the first instruction decoder means; reading means for receiving an instruction from said second instruction decoder means when said parallel-decodable instruction is a data transmission instruction and for reading data from the memory unit according to the data transmission instruction; operating means for performing an operation to be completed by using a plurality of registers according to the subsequent instructions; delay control means for delay operation of the operating means until necessary data for the operation are obtained in response to instructions decoded by the first instruction decoder means and the second instruction decoder means; and writing means for writing data into the memory unit according to the data transmission instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |