EP0260409A2
Expired / Lapsed
EP
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Data processing system with two execution units
Assignee: International Business Machines Corp
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Filing: 1987-07-24
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Granted: —
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Expires: 2007-07-24
Abstract
Abstract A scheme for enhancing the performance of a VLSI processor of the reduced instruction set computer (RISC) type by executing two instructions simultaneously in the two execution units of the processor is disclosed. There is very little increase in the cost of hardware. Three embodiments are presented with different cost and performance capabilities. The first embodiment has an instruction input to an instruction buffer (10) and two sets of control ROSs (40 and 42) and control registers (64 and 65). The control ROS and control register which is chosen depends on which instruction execution unit is to execute the instruction. Data inputs to the execution units is from a register file (48) which has an additional pair of outputs (51) and (53) that provide the data paths for simultaneous execution of instructions by the execution units. Execution unit I has an arithmetic and logic unit (ALU) (24), while execution unit II has a rotate (26) and mask generator (31). Load balancing between the two execution units can be performed by adding a multiplier (60) and divider (62) to execution unit II. In the second embodiment of the invention, the same approach is used, and further load balancing is achieved by incorporating an adder (78) into execution unit II. The adder (78) is used to perform address calculations to speed up the load, store and branch instructions. In the third embodiment, an additional ALU (90) is added to execution unit II to allow the instruction processing to be further balanced between the two execution units.
Inventors
- 👤 Chiao-Mei Chuang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 12:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
326 words
Data processing system having instruction handling apparatus comprising an instruction buffer (10), control read only storage (40) and control registers (44) and instruction execution apparatus comprising a register file (48) having inputs and outputs, one of said inputs (15) being connected to receive data from memory, staging registers (18,20,22) connected to said register file outputs, and first and second execution units, said first execution unit comprising an arithmetic logic unit (24) having inputs connected to two of said staging registers, said second execution unit comprising a rotator (26) and mask generator means (31) having inputs connected to three of said staging registers, said arithmetic logic unit and said rotator and mask generator means having outputs, a first output register (66) for receiving the outputs of said arithmetic logic unit or said rotator and mask generator means and supplying an input to said register file wherein the system performs sequential data manipulations under the control of instructions, said instructions being executed by one of said first and second execution units, the data processing system being characterized in that said control read only storage comprises first and second segments (40,42) for respectively receiving instruction sets for said first and second execution units; said instruction handling apparatus further includes means (44,46) for routing instructions from said first segment of said control read only storage to said first execution unit and means for routing instructions from said second segment of said control read only storage to said second execution unit; a second output register (68) is provided, the outputs from said arithmetic logic unit and said rotate and mask generator means being separately connected to a respective one of said first and second output registers (66,68), outputs from each of said output registers being connected to inputs (17,56) of said register file; and said first execution unit and said second execution unit simultaneously receive outputs from said staging registers connected to outputs of said register file and executing in parallel.
Claim 2
Dependent Claim
326 words
Data processing system having instruction handling apparatus comprising an instruction buffer (10), control read only storage (40) and control registers (44) and instruction execution apparatus comprising a register file (48) having inputs and outputs, one of said inputs (15) being connected to receive data from memory, staging registers (18,20,22) connected to said register file outputs, and first and second execution units, said first execution unit comprising an arithmetic logic unit (24) having inputs connected to two of said staging registers, said second execution unit comprising a rotator (26) and mask generator means (31) having inputs connected to three of said staging registers, said arithmetic logic unit and said rotator and mask generator means having outputs, a first output register (66) for receiving the outputs of said arithmetic logic unit or said rotator and mask generator means and supplying an input to said register file wherein the system performs sequential data manipulations under the control of instructions, said instructions being executed by one of said first and second execution units, the data processing system being characterized in that said control read only storage comprises first and second segments (40,42) for respectively receiving instruction sets for said first and second execution units; said instruction handling apparatus further includes means (44,46) for routing instructions from said first segment of said control read only storage to said first execution unit and means for routing instructions from said second segment of said control read only storage to said second execution unit; a second output register (68) is provided, the outputs from said arithmetic logic unit and said rotate and mask generator means being separately connected to a respective one of said first and second output registers (66,68), outputs from each of said output registers being connected to inputs (17,56) of said register file; and said first execution unit and said second execution unit simultaneously receive outputs from said staging registers connected to outputs of said register file and executing in parallel.
Claim 3
Dependent Claim
75 words
The data processing system of claim 1, wherein are provided: at least one arithmetic function unit (60,62) in said second execution unit, said arithmetic function unit having inputs connected to two of said three staging registers and providing an output; and a multiplexer (63) connected to recieve the outputs of said rotate and mask generator means and said at least one arithmetic function unit and supplying one of said outputs to said second output register.
Claim 4
Dependent Claim
23 words
The data processing system of claim 2, wherein said at least one arithmetic function unit comprises a multiplier (60) and a divider (62).
Claim 5
Dependent Claim
39 words
The data processing system of claim 2 or 3, wherein said at least one arithmetic function unit comprises an adder (78), said adder being used to compute the addresses of instructions to speed up load, store and branch instructions.
Claim 6
Dependent Claim
42 words
The data processing system of claim 2, wherein said at least one arithmetic function unit comprises a second arithmetic logic unit (90) whereby code scheduling and load balancing of the instruction load may be performed between said first and second execution units.
Claim 7
Dependent Claim
78 words
The data processing system of one of the claims 1-5, further comprising two latches (110,112) connected to two outputs of said register file (48), said two latches having outputs connected to said two of said staging registers, said three of said staging registers being directly connected to three outputs of said register file including the two outputs connected to said two latches whereby said register file makes two accesses to memory for each clock cycle of said computer.
Claim 8
Dependent Claim
72 words
The data processing system of one of the claims 1-6, wherein said register file (48) has at least five outputs (19,21,23,51,53) and wherein there are at least five staging registers (18,20,22,50,52), one staging register of each of said outputs, and wherein said two (18,20) of said staging registers are connected exclusively to said first execution unit and said three (22,50,52) of said staging registers are connected exclusively to said second execution unit.
Claim 9
Dependent Claim
20 words
The data processing system of one of the claims 1-7 characterized in that it forms a reduced instruction set computer.
References Cited (Backward Citations)
No citation records indexed.
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