Patent US5200360A successfully refreshed from Google Patents.
US5200360A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for reducing selectivity loss in selective tungsten deposition
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1991-11-12
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Granted: 1993-04-06
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Expires: 2011-11-12
Abstract
Abstract A method of forming a plug for electrical connection between two metallic layers on an integrated circuit substrate includes retaining an antinucleation resist layer atop an insulator layer through which the plug is to be formed. After a contact hole is etched through the insulator layer, the antinucleation resist layer is baked. Cleaning of an area exposed by said contact hole in order to minimize contact resistance occurs during a two step process of argon sputter etching and oxygen plasma descumming the exposed area. Because the argon sputter etch and the oxygen plasma descum uncover an annular region about the contact hole, a concentration of phosphorous within the insulator layer and a low temperature selective deposition are used to reduce the occurrence of unwanted nucleation. After selective deposition, the antinucleation resist layer is stripped and an upper metallic layer is formed.
Inventors
- 👤 Donald R. Bradbury
- 👤 Gary W. Ray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; Y; Y10; Y10S; Y10S438/00; Y10S438/906; Y10S438/978
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
136 words
A method of providing a plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming an insulator layer on a metallic layer; forming an antinucleation resist layer on said insulator layer; forming a contact hole through said antinucleation resist layer and said insulator layer; baking said antinucleation resist layer, effective for thermosetting said antinucleation resist layer; removing an upper portion of said antinucleation resist layer, said removing including, exposing a region of said insulator layer about said contact hole, retaining a lower portion of said antinucleation resist layer to cover the remainder of said insulator layer, and argon sputter etching and oxygen plasma descumming said metallic layer to the extent exposed by said forming of said contact hole; selectively depositing tungsten into said contact hole; and removing said antinucleation resist layer.
Claim 2
Independent Claim
136 words
A method of providing a plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming an insulator layer on a metallic layer; forming an antinucleation resist layer on said insulator layer; forming a contact hole through said antinucleation resist layer and said insulator layer; baking said antinucleation resist layer, effective for thermosetting said antinucleation resist layer; removing an upper portion of said antinucleation resist layer, said removing including, exposing a region of said insulator layer about said contact hole, retaining a lower portion of said antinucleation resist layer to cover the remainder of said insulator layer, and argon sputter etching and oxygen plasma descumming said metallic layer to the extent exposed by said forming of said contact hole; selectively depositing tungsten into said contact hole; and removing said antinucleation resist layer.
Claim 3
Independent Claim
119 words
A method of providing a plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming a metallic layer; forming a dielectric layer on said metallic layer; depositing a resist layer on said dielectric layer; etching contact holes in said dielectric layer using said resist layer; baking said resist layer; removing an upper portion of said resist layer, effective for leaving a lower portion of said resist layer covering said dielectric layer; selectively depositing tungsten in said contact holes; removing said lower portion of said resist layer; and said baking is conducted at a temperature at least as great as the temperature reached in said step of selectively depositing tungsten for at least one hour.
Claim 4
Independent Claim
119 words
A method of providing a plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming a metallic layer; forming a dielectric layer on said metallic layer; depositing a resist layer on said dielectric layer; etching contact holes in said dielectric layer using said resist layer; baking said resist layer; removing an upper portion of said resist layer, effective for leaving a lower portion of said resist layer covering said dielectric layer; selectively depositing tungsten in said contact holes; removing said lower portion of said resist layer; and said baking is conducted at a temperature at least as great as the temperature reached in said step of selectively depositing tungsten for at least one hour.
Claim 5
Independent Claim
122 words
A method of providing an electrically conductive plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming a metallic layer; forming a dielectric layer on said metallic layer; depositing a resist layer on said dielectric layer; etching contact holes in said dielectric layer using said resist layer; baking said resist layer; removing an upper portion of said resist layer, effective for leaving a lower portion of said resist layer covering said dielectric layer, wherein said step of removing includes argon sputter etching and oxygen plasma descumming said metallic layer to the extent exposed by said step of etching said contact holes; selectively depositing tungsten in said contact holes; and removing said lower portion of said resist layer.
Claim 6
Independent Claim
122 words
A method of providing an electrically conductive plug for electrical connection to a metallic layer on an integrated circuit substrate comprising: forming a metallic layer; forming a dielectric layer on said metallic layer; depositing a resist layer on said dielectric layer; etching contact holes in said dielectric layer using said resist layer; baking said resist layer; removing an upper portion of said resist layer, effective for leaving a lower portion of said resist layer covering said dielectric layer, wherein said step of removing includes argon sputter etching and oxygen plasma descumming said metallic layer to the extent exposed by said step of etching said contact holes; selectively depositing tungsten in said contact holes; and removing said lower portion of said resist layer.
Claim 7
Independent Claim
124 words
A method of fabricating an integrated circuit comprising: forming a metallic layer; forming an insulator layer having a concentration of phosphorous on said metallic layer; forming a photoresist layer on said insulator layer; photolithographically etching a contact hole on said insulator layer using said photoresist layer, effective for exposing an area of said metallic layer; baking said photoresist layer; cleaning said exposed area of said metallic layer, said cleaning including, uncovering a region atop said insulator layer about said contact hole while leaving the remainder of said insulator layer covered by said photoresist layer, and sputter etching and oxygen plasma descumming said exposed area of said metallic layer; selectively depositing tungsten onto said exposed area of said metallic layer; and removing said photoresist layer.
Claim 8
Independent Claim
124 words
A method of fabricating an integrated circuit comprising: forming a metallic layer; forming an insulator layer having a concentration of phosphorous on said metallic layer; forming a photoresist layer on said insulator layer; photolithographically etching a contact hole on said insulator layer using said photoresist layer, effective for exposing an area of said metallic layer; baking said photoresist layer; cleaning said exposed area of said metallic layer, said cleaning including, uncovering a region atop said insulator layer about said contact hole while leaving the remainder of said insulator layer covered by said photoresist layer, and sputter etching and oxygen plasma descumming said exposed area of said metallic layer; selectively depositing tungsten onto said exposed area of said metallic layer; and removing said photoresist layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-04-05 | 1996-10-05 | 1997-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-05 | 2000-10-05 | 2001-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-05 | 2004-10-05 | 2005-04-06 | $7700.00 | Window Closed / Lapsed |