Methods for inhibiting outgrowth of silicide in self-aligned silicide process

Claim 1

A method for preparing silicide contact areas on integrated circuit devices which inhibit formation of short circuit paths between adjacent silicide contact areas over silicon dioxide spacer regions formed between said silicide contact areas, said method comprising the steps of: (a) fabricating an integrated circuit structure having a plurality of upper and lower silicon contact areas situated on a silicon substrate, each said lower silicon contact area having a top and a bottom surface, each said upper silicon contact area having a top, a bottom and multiple vertical surfaces, said upper silicon contact area being vertically offset from each said lower silicon contact area by a substantially horizontally-oriented offset area, each said offset area comprising silicon dioxide and being situated substantially under the entire bottom surface of one of said upper silicon contact areas, and at least partially over the top surface of one of said lower silicon contact areas; (b) forming silicon dioxide spacer regions on said silicon substrate, each said silicon dioxide spacer region being in contact with: the top surface of one of said lower silicon contact areas, at least one of said vertical surfaces of one of said upper silicon contact areas, and below the top surface of one of said upper silicon contact areas, and each said offset area; (c) depositing a metal film directly over and onto the integrated circuit structure, said top surface of each said lower silicon contact area, said top and vertical surfaces of each said upper silicon contact area, and said silicon dioxide spacer regions, said metal being capable of reacting with silicon to form a metal silicide and with nitrogen to form a metal nitride, said metal nitride being capable of inhibiting diffusion of silicon; (d) depositing a nitrogen rich metal nitride film over said metal film; (e) annealing said integrated circuit structure and forming a plurality of vertically offset upper and lower metal silicide regions, each said lower metal silicide region having: a top surface and being substantially over the entire top surface of one of said lower silicon contact areas and partially over the silicon spacer region that is on said top surface of said one of said lower silicon contact areas, each said upper metal silicide region having a top surface and being substantially over the entire top surface of one of said upper silicon contact areas, substantially above each said vertical surface of said one of said upper silicon contact areas and substantially above and completely out of contact with the silicon dioxide spacer region contacting said vertical surfaces of said one of said upper silicon contact areas, and forming metal nitride regions: in said metal film, substantially entirely over the top surface of each said upper and lower metal silicide regions, and both in contact with and substantially entirely over each said silicon dioxide spacer regions, so as to inhibit diffusion of silicon from said silicon contact areas not covered by said spacer oxide regions; and (f) etching excess metal rich metal nitride film and metal film from said top surfaces of said upper and lower metal silicide regions, and from said silicon dioxide spacer regions, and generally from said integrated circuit structure.

Claim 2

A method for preparing silicide contact areas on integrated circuit devices which inhibit formation of short circuit paths between adjacent silicide contact areas over silicon dioxide spacer regions formed between said silicide contact areas, said method comprising the steps of: (a) fabricating an integrated circuit structure having a plurality of upper and lower silicon contact areas situated on a silicon substrate, each said lower silicon contact area having a top and a bottom surface, each said upper silicon contact area having a top, a bottom and multiple vertical surfaces, said upper silicon contact area being vertically offset from each said lower silicon contact area by a substantially horizontally-oriented offset area, each said offset area comprising silicon dioxide and being situated substantially under the entire bottom surface of one of said upper silicon contact areas, and at least partially over the top surface of one of said lower silicon contact areas; (b) forming silicon dioxide spacer regions on said silicon substrate, each said silicon dioxide spacer region being in contact with: the top surface of one of said lower silicon contact areas, at least one of said vertical surfaces of one of said upper silicon contact areas, and below the top surface of one of said upper silicon contact areas, and each said offset area; (c) depositing a metal film directly over and onto the integrated circuit structure, said top surface of each said lower silicon contact area, said top and vertical surfaces of each said upper silicon contact area, and said silicon dioxide spacer regions, said metal being capable of reacting with silicon to form a metal silicide and with nitrogen to form a metal nitride, said metal nitride being capable of inhibiting diffusion of silicon; (d) depositing a nitrogen rich metal nitride film over said metal film; (e) annealing said integrated circuit structure and forming a plurality of vertically offset upper and lower metal silicide regions, each said lower metal silicide region having: a top surface and being substantially over the entire top surface of one of said lower silicon contact areas and partially over the silicon spacer region that is on said top surface of said one of said lower silicon contact areas, each said upper metal silicide region having a top surface and being substantially over the entire top surface of one of said upper silicon contact areas, substantially above each said vertical surface of said one of said upper silicon contact areas and substantially above and completely out of contact with the silicon dioxide spacer region contacting said vertical surfaces of said one of said upper silicon contact areas, and forming metal nitride regions: in said metal film, substantially entirely over the top surface of each said upper and lower metal silicide regions, and both in contact with and substantially entirely over each said silicon dioxide spacer regions, so as to inhibit diffusion of silicon from said silicon contact areas not covered by said spacer oxide regions; and (f) etching excess metal rich metal nitride film and metal film from said top surfaces of said upper and lower metal silicide regions, and from said silicon dioxide spacer regions, and generally from said integrated circuit structure.

Claim 11

A method for preparing titanium silicide contact areas on MOS transistor structures which inhibit formation of titanium silicide short circuit paths between the gate electrode regions and the source/drain regions of the MOS transistor structure, the method comprising the steps of: (a) fabricating a MOS transistor structure having an upper silicon contact region comprising a silicon gate electrode region, and two lower silicon contact regions comprising respectively a source and a drain region, said lower silicon contact, gate electrode, source and drain regions all having top and bottom surfaces, said gate electrode region also having a plurality of vertical surfaces and being vertically offset from said source region and from drain region by a substantially horizontally-oriented offset area, said offset area comprising silicon dioxide and being substantially under the entire bottom surface of said gate electrode region and at least partially over the top surface of a lower silicon contact region; (b) forming a first and a second spacer oxide regions, said first spacer oxide region being in contact with the top surface of the source region, at least one vertical surface of the gate electrode region, the offset area, said first spacer oxide region being situated below the top surface of the gate electrode region said second spacer oxide region being in contact with the top surface of the drain region, at least one vertical surface of the gate electrode region, the offset area, said second spacer oxide region being situated below the top surface of the gate electrode region; (c) depositing a titanium film directly over and onto said MOS transistor structure, said top surface of both said source and drain regions, said top and vertical surfaces of said gate electrode region, and said spacer oxide regions; (d) depositing a nitrogen-rich titanium nitride film over said titanium film; (e) annealing said MOS transistor structure to form: a first titanium silicide region having a top surface and being substantially over the entire top surface of said source region and partially over the spacer oxide region on said source region, a second titanium silicide region having a top surface and being substantially over the entire top surface of said drain region and partially over the spacer oxide region on said drain region, a third titanium silicide region having a top surface and being substantially over the entire top surface of said gate electrode region, substantially above said vertical surfaces of said gate electrode region, and substantially above and completely out of contact with the spacer oxide regions contacting said vertical surfaces of said gate electrode region, and to form titanium nitride regions in said titanium film, substantially entirely the top surface of said source, drain, and gate electrode regions, and both in contact with and substantially entirely over said first and second spacer oxide regions so as to inhibit diffusion of silicon between said gate electrode region and said source and drain regions not covered by said spacer oxide regions; and (f) etching excess titanium nitride and titanium from said top surfaces of said source, drain, and gate electrode regions, said spacer oxide regions, and said integrated circuit structure,

Claim 12

A method for preparing titanium silicide contact areas on MOS transistor structures which inhibit formation of titanium silicide short circuit paths between the gate electrode regions and the source/drain regions of the MOS transistor structure, the method comprising the steps of: (a) fabricating a MOS transistor structure having an upper silicon contact region comprising a silicon gate electrode region, and two lower silicon contact regions comprising respectively a source and a drain region, said lower silicon contact, gate electrode, source and drain regions all having top and bottom surfaces, said gate electrode region also having a plurality of vertical surfaces and being vertically offset from said source region and from drain region by a substantially horizontally-oriented offset area, said offset area comprising silicon dioxide and being substantially under the entire bottom surface of said gate electrode region and at least partially over the top surface of a lower silicon contact region; (b) forming a first and a second spacer oxide regions, said first spacer oxide region being in contact with the top surface of the source region, at least one vertical surface of the gate electrode region, the offset area, said first spacer oxide region being situated below the top surface of the gate electrode region said second spacer oxide region being in contact with the top surface of the drain region, at least one vertical surface of the gate electrode region, the offset area, said second spacer oxide region being situated below the top surface of the gate electrode region; (c) depositing a titanium film directly over and onto said MOS transistor structure, said top surface of both said source and drain regions, said top and vertical surfaces of said gate electrode region, and said spacer oxide regions; (d) depositing a nitrogen-rich titanium nitride film over said titanium film; (e) annealing said MOS transistor structure to form: a first titanium silicide region having a top surface and being substantially over the entire top surface of said source region and partially over the spacer oxide region on said source region, a second titanium silicide region having a top surface and being substantially over the entire top surface of said drain region and partially over the spacer oxide region on said drain region, a third titanium silicide region having a top surface and being substantially over the entire top surface of said gate electrode region, substantially above said vertical surfaces of said gate electrode region, and substantially above and completely out of contact with the spacer oxide regions contacting said vertical surfaces of said gate electrode region, and to form titanium nitride regions in said titanium film, substantially entirely the top surface of said source, drain, and gate electrode regions, and both in contact with and substantially entirely over said first and second spacer oxide regions so as to inhibit diffusion of silicon between said gate electrode region and said source and drain regions not covered by said spacer oxide regions; and (f) etching excess titanium nitride and titanium from said top surfaces of said source, drain, and gate electrode regions, said spacer oxide regions, and said integrated circuit structure,

Claim 18

A method for preparing titanium silicide contact areas on MOS transistor structures which inhibit formation of titanium silicide short circuit paths between the gate electrode regions and the source/drain regions of the MOS transistor structure, the method comprising the steps of: (a) fabricating a MOS transistor structure having an upper silicon contact region comprising a silicon gate electrode region,and two lower silicon contact regions comprising respectively a source and a drain region, said lower silicon contact, gate electrode, source and drain regions all having top and bottom surfaces, said gate electrode region also having a plurality of vertical surfaces and being vertically offset from said source region and from drain region by a substantially horizontally-oriented offset area, said offset area comprising silicon dioxide and being substantially under the entire bottom surface of said gate electrode region and at least partially over the top surface of a lower silicon contact region; (b) forming a first and a second spacer oxide regions, said first spacer oxide region being in contact with the top surface of the source region, at least one vertical surface of the gate electrode region, the offset area, said first spacer oxide region being situated below the top surface of the gate electrode region, said second spacer oxide region being in contact with the top surface of the drain region, at least one vertical surface of the gate electrode region, the offset area, said second spacer oxide region being situated below the top surface of the gate electrode region; (c) selectively depositing a silicon layer over said top surface of both said source and drain regions, said top and vertical surfaces of said gate electrode region, said spacer oxide regions, and over said MOS transistor structure; (d) depositing a titanium film over said MOS transistor structure, wherein said titanium film is deposited by sputtering; (e) depositing a nitrogen-rich titanium nitride film over said titanium film wherein the ratio of nitrogen to titanium in said nitrogen-rich titanium nitride film is in the range from about 1 to about 2 and wherein said nitrogen-rich titanium nitride film is deposited by reactive sputtering; (f) annealing said MOS transistor structure to form: a first titanium silicide region having a top surface and being substantially over the entire top surface of said source region and partially over the spacer oxide region on said source region, a second titanium silicide region having a top surface and being substantially over the entire top surface of said drain region and partially over the spacer oxide region on said drain region, a third titanium silicide region having a top surface and being substantially over the entire top surface of said gate electrode region, substantially above said vertical surfaces of said gate electrode region, and substantially above and completely out of contact with the spacer oxide regions contacting said vertical surfaces of said gate electrode region, and to form titanium nitride regions in said titanium film, substantially entirely the top surface of said source, drain, and gate electrode regions, and both in contact with and substantially entirely over said first and second spacer oxide regions so as to inhibit diffusion of silicon from said gate electrode and said source/drain regions not covered by said spacer oxide regions; and (g) etching excess titanium nitride and titanium from said MOS transistor structure, said top surfaces of said source, drain, and gate electrode regions, and from said spacer oxide regions.

Claim 19

A method for preparing titanium silicide contact areas on MOS transistor structures which inhibit formation of titanium silicide short circuit paths between the gate electrode regions and the source/drain regions of the MOS transistor structure, the method comprising the steps of: (a) fabricating a MOS transistor structure having an upper silicon contact region comprising a silicon gate electrode region,and two lower silicon contact regions comprising respectively a source and a drain region, said lower silicon contact, gate electrode, source and drain regions all having top and bottom surfaces, said gate electrode region also having a plurality of vertical surfaces and being vertically offset from said source region and from drain region by a substantially horizontally-oriented offset area, said offset area comprising silicon dioxide and being substantially under the entire bottom surface of said gate electrode region and at least partially over the top surface of a lower silicon contact region; (b) forming a first and a second spacer oxide regions, said first spacer oxide region being in contact with the top surface of the source region, at least one vertical surface of the gate electrode region, the offset area, said first spacer oxide region being situated below the top surface of the gate electrode region, said second spacer oxide region being in contact with the top surface of the drain region, at least one vertical surface of the gate electrode region, the offset area, said second spacer oxide region being situated below the top surface of the gate electrode region; (c) selectively depositing a silicon layer over said top surface of both said source and drain regions, said top and vertical surfaces of said gate electrode region, said spacer oxide regions, and over said MOS transistor structure; (d) depositing a titanium film over said MOS transistor structure, wherein said titanium film is deposited by sputtering; (e) depositing a nitrogen-rich titanium nitride film over said titanium film wherein the ratio of nitrogen to titanium in said nitrogen-rich titanium nitride film is in the range from about 1 to about 2 and wherein said nitrogen-rich titanium nitride film is deposited by reactive sputtering; (f) annealing said MOS transistor structure to form: a first titanium silicide region having a top surface and being substantially over the entire top surface of said source region and partially over the spacer oxide region on said source region, a second titanium silicide region having a top surface and being substantially over the entire top surface of said drain region and partially over the spacer oxide region on said drain region, a third titanium silicide region having a top surface and being substantially over the entire top surface of said gate electrode region, substantially above said vertical surfaces of said gate electrode region, and substantially above and completely out of contact with the spacer oxide regions contacting said vertical surfaces of said gate electrode region, and to form titanium nitride regions in said titanium film, substantially entirely the top surface of said source, drain, and gate electrode regions, and both in contact with and substantially entirely over said first and second spacer oxide regions so as to inhibit diffusion of silicon from said gate electrode and said source/drain regions not covered by said spacer oxide regions; and (g) etching excess titanium nitride and titanium from said MOS transistor structure, said top surfaces of said source, drain, and gate electrode regions, and from said spacer oxide regions.