← Back to Patent Explorer
US5187111A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing Schottky barrier gate FET

Assignee: Toshiba Corp
•
Filing: 1991-04-23
•
Granted: 1993-02-16
•
Expires: 2011-04-23
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The method of manufacturing the SB FET according to the present invention includes a first step of forming a first WN metal film on a GaAs substrate, a second step of forming a first ion-implanted region within the GaAs substrate, by ion implantation of n-type impurities, a third step of forming a second Mo metal film, a fourth step of forming second and third ion-implanted regions adjacent to said first ion-implanted region, within the GaAs substrate, and a fifth step of activating said first, second, and third ion-implanted regions. In the ion implantation of the second step, impurity ions are implanted into the GaAs substrate, through the first metal film. In the fifth step, the first metal film serves as a protective film during the activation of the first, second, and third ion-implanted regions.

Inventors

  • 👤 Takeshi Nogami
  • 👤 Hiroshi Iwasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:28
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10P; H10P30/00; H10P30/20; H10P30/22; Y; Y10; Y10S; Y10S148/00; Y10S148/14

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 197 words
A method of manufacturing a Schottky barrier gate type FET comprising: a first step of forming a first film, made of a refractory metal or refractory metal compound, on a semiconductor substrate; a second step of forming a first ion-implanted region in said semiconductor substrate by an ion-implantation process during which impurity ions pass through said first film; a third step, independent of said second step, of forming second and third ion-implanted regions in said semiconductor substrate by an ion-implantation process during which impurity ions pass through said first film, said second and third ion-implanted regions being adjacent to said first ion-implanted region; a fourth step of forming a channel region, source region, and drain region, by annealing to activate said first, second, and third ion-implanted region using said first film as a protective film, and bringing said first film in Schottky contact with said channel region; and a fifth step of forming a Schottky gate electrode, in Schottky contact with said channel region, by patterning said first after said channel, source, and drain regions have been formed, with said first film being selectively maintained to prevent exposure of the channel region underlying the Schottky gate electrode.
Claim 2
Independent Claim 197 words
A method of manufacturing a Schottky barrier gate type FET comprising: a first step of forming a first film, made of a refractory metal or refractory metal compound, on a semiconductor substrate; a second step of forming a first ion-implanted region in said semiconductor substrate by an ion-implantation process during which impurity ions pass through said first film; a third step, independent of said second step, of forming second and third ion-implanted regions in said semiconductor substrate by an ion-implantation process during which impurity ions pass through said first film, said second and third ion-implanted regions being adjacent to said first ion-implanted region; a fourth step of forming a channel region, source region, and drain region, by annealing to activate said first, second, and third ion-implanted region using said first film as a protective film, and bringing said first film in Schottky contact with said channel region; and a fifth step of forming a Schottky gate electrode, in Schottky contact with said channel region, by patterning said first after said channel, source, and drain regions have been formed, with said first film being selectively maintained to prevent exposure of the channel region underlying the Schottky gate electrode.
Claim 3
Dependent Claim 41 words
A method according to claim 1, further comprising a sixth step of forming a second film, made of a refractory metal or a refractory metal compound, on the first film, said second film forming a portion of said Schottky gate electrode.
Claim 4
Dependent Claim 33 words
A method according to claim 1, wherein said fourth step includes a first substep of simultaneously annealing said first, second, and third ion-implanted regions, said first film being used as a protective film.
Claim 5
Dependent Claim 13 words
A method according to claim 1, wherein said semiconductor substrate is gallium arsenide.
Claim 6
Dependent Claim 18 words
A method according to claim 1, wherein said first film is formed of tungsten nitride or tungsten silicide.

References Cited (Backward Citations)

US4330343A Cited
US4601095A Cited
US4546540A Cited
US4642879A Cited
US4581076A Cited
EP0213919A2 Cited
US4735913A Cited
JPS6425528A Cited
US4929567A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-02-16 1996-08-17 1997-02-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-02-16 2000-08-17 2001-02-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-02-16 2004-08-17 2005-02-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag