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JPS6425528A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1987-07-22
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Granted: —
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Expires: 2007-07-22
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Abstract

Abstract PURPOSE:To decrease the ohmic contact resistance of a compound semiconductor element and to improve the electric characteristics of an element, by implanting high concentration impurities from the surface of a low resistance semiconductor layer, which is epitaxially grown, to the interface with the compound semiconductor layer, and performing heat treatment. CONSTITUTION:As a low resistance semiconductor layer 6, an N<+> type Ge layer is formed by an organic metal vapor growth method, or an N<+> InGaAs layer is formed by a molecular beam epitaxial growing method. The thickness of the low resistance semiconductor layer 6 is sufficiently thinner than the thickness of an SiO2 film 3. Then, Si ions are implanted into the entire surface. At this time, the Si ions 10 are implanted also into an N-type GaAs layer 2 through the low resistance semiconductor layer 6. After the implantation of the Si ions, heat treatment is performed in an As atmosphere. The implanted Si is electrically activated. Ohmic electrodes 7 and a Schottky electrode 8 are formed, and a MESFET of GaAs is formed. Thus, the contact resistance at the interface between the compound semiconductor 2 and the low resistance semiconductor layer 6, which is grown thereon, can be largely reduced. A compound semiconductor element having excellent ohmic contact can be readily formed.

Inventors

  • 👤 Kaoru Inoue

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 05:31
CPC Classifications
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