Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance

Claim 1

A semiconductor package for supporting and interconnecting semiconductor chips, each of said chips having respective chip contacts on a contact surface, said package also including a substrate having substrate contacts on a contact surface and a plurality of interposer modules each of which is disposed between a chip in said package and said substrate contact surface, each of said interposer modules having respective upper and lower opposed surfaces and a planar size which allows substantial wall-to-wall placement of said semiconductor chips and interposer modules and comprising: a first plurality of contacts on said respective upper surface, said first plurality of contacts positioned to mate with said respective chip contacts; a second plurality of contacts on said respective lower surface, said second plurality of contacts positioned to mate with said substrate contacts; a set of conductive vias in each of said interposer modules for connecting said first plurality of contacts with a first subset of said second plurality of contacts; layers of engineering change wiring positioned in said plurality of interposer modules and adjacent said respective lower surfaces said engineering change wiring including at least one layer of parallel conductors connected to a second subset of said second plurality of contacts, said parallel conductors passing adjacent a plurality of conductive vias and selectively interconnectable therewith to achieve an electrical connection between a respective via and a respective one of said second plurality of contacts in said second subset; and distributed capacitive means positioned within each of said interposer modules adjacent said upper surface and connected to selected ones of said first plurality of contacts.