Memory device having bit lines over a field oxide

Claim 2

A memory cell in a semiconductor substrate comprising: a field oxide layer on the surface of said substrate, said field oxide layer patterned to selectively expose a surface of said semiconductor substrate and including a region defined by edges; a capacitor having a capacitor plate material therein for storage of electrical charge within said capacitor; a pass gate transistor having a source and a drain, the drain of said transistor operably connected to said capacitor so as to transfer signals between said capacitor and a bit line; and said bit line covering said region of said field oxide layer, said bit line extending sufficiently beyond said edges of said region such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of said pass gate transistor, and whereby said bit line has substantially no other contact with said substrate.

Claim 3

The memory cell as defined in claim 1, wherein said capacitor plate material is recessed from the surface of said substrate.

Claim 4

The memory cell as defined in claim 1, further comprising a conductive layer connecting said capacitor plate and the drain of said pass gate transistor.

Claim 5

The memory cell as defined in claim 3, wherein said capacitor plate material is recessed from the surface of said substrate.

Claim 6

The memory cell as defined in claim 1, wherein said capacitor is a trench capacitor.

Claim 7

A memory device comprising: a semiconductor substrate; a field oxide layer on the surface of said semiconductor substrate, said field oxide layer patterned to selectively expose the surface of said semiconductor substrate and including a plurality of regions defined by edges; a plurality of trench capacitors formed in said substrate, each of said trenches having a capacitor plate material therein for storing charge within said trench; a plurality of pass gate transistors each having a source and drain, the drain of said transistors operably connected to an associated one of said trench capacitors so as to transfer signals between a selected one of said trench capacitors and an associated bit line, a bit line covering said plurality of regions of said field oxide layer, said bit line having a size selected to extend sufficiently beyond said edges of said regions such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of its associated one of said pass gate transistors, and whereby said bit line has substantially no other contact with said substrate.

Claim 8

A memory device comprising: a semiconductor substrate; a field oxide layer on the surface of said semiconductor substrate, said field oxide layer patterned to selectively expose the surface of said semiconductor substrate and including a plurality of regions defined by edges; a plurality of trench capacitors formed in said substrate, each of said trenches having a capacitor plate material therein for storing charge within said trench; a plurality of pass gate transistors each having a source and drain, the drain of said transistors operably connected to an associated one of said trench capacitors so as to transfer signals between a selected one of said trench capacitors and an associated bit line, a bit line covering said plurality of regions of said field oxide layer, said bit line having a size selected to extend sufficiently beyond said edges of said regions such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of its associated one of said pass gate transistors, and whereby said bit line has substantially no other contact with said substrate.

Claim 9

The memory device as defined in claim 6, wherein said capacitor plate material is recessed from the surface of said substrate.

Claim 10

The memory cell as defined in claim 6, further comprising a conductive layer connecting said capacitor plate material and the drain of its associated one of said pass gate transistors.

Claim 11

The memory cell as defined in claim 8, wherein said capacitor plate material is recessed from the surface of said substrate.