Semiconductor memory device having substrate isolation of a switching transistor and storage capacitor

Claim 2

In a dynamic semiconductor memory of a type forming an array of vertical integrated transistors within a common substrate having a major surface, wherein each of said vertical integrated transistors comprises vertically orientated semiconductor layers defining source and drain regions, and a trench extending into said substrate at said source and drain regions to define a channel region, a lowermost one of said layers of said vertical integrated transistor in said substrate formed of a polycrystal semiconductor layer and defining one of the source region and drain region: the improvement comprising a first insulating layer underlying said polycrystal semiconductor layer and a second insulating layer formed on said polycrystal semiconductor layer above a portion of the substrate surrounding said trench surrounding said trench, and extending outside said trench on the major surface of said substrate to isolate said vertical integrated transistor from said substrate and to reduce soft errors of said transistor by electron-hole pairs produced in said substrate as a result of ambient alpha particles penetrating said substrate.

Claim 3

A dynamic semiconductor memory having substrate isolation in accordance with claim 1, comprising: an isolation insulating film formed on said first insulating layer and isolating said polycrystal semiconductor layer from a polycrystal semiconductor layer of adjacent cells.

Claim 4

A dynamic semiconductor memory having substrate isolation in accordance with claim 1, comprising: an electrode provided so as to electrically couple said channel region to a word line.

Claim 5

A dynamic semiconductor memory having substrate isolation in accordance with claim 1, wherein said polycrystal semiconductor layer comprises a diffused layer.

Claim 6

A dynamic semiconductor memory having substrate isolation in accordance with claim 1, comprising: a low resistive portion formed on said second insulating film and electrically coupled to said channel region, said low resistive portion comprising a bit line.

Claim 7

The semiconductor memory device in accordance with claim 1, wherein the material of said first and second insulating layers is SiO 2 .

Claim 8

A semiconductor memory device, comprising: a silicon single crystal substrate having a major surface and a trench portion formed therein, the trench portion defined by a wall and bottom surface; a first insulating layer on the wall and bottom surface of said trench portion and extending outside the trench portion on the major surface of said substrate; said trench portion being filled in the inside thereof with a material of a first conductivity type up to the depth of said first insulating layer; a first single crystal silicon layer formed on said first insulating layer; diffusion regions in said first single crystal silicon layer serving as source and drain regions formed on said first insulating layer and said material of the first conductivity type by doping said first single crystal silicon layer with a first impurity to a high degree of concentration; a second insulating layer formed on said first single crystal silicon layer; a low resistive portion serving as a source or drain region formed on said second insulating layer; a second single crystal silicon layer formed along inner surfaces of said second insulating layer and said low resistive portion; a gate insulating layer formed on said low resistive portion and along said surface of said second single crystal silicon layer and said diffused region and having a trench portion on said material of a first conductivity type; and a gate electrode formed by filling a material of a first conductivity type in the trench portion of said gate insulating layer above the trench portion of said substrate; said low resistive portion being electrically coupled to a bit line and said gate electrode being connected to a word line.

Claim 9

A semiconductor memory device, comprising: a silicon single crystal substrate having a major surface and a trench portion formed therein, the trench portion defined by a wall and bottom surface; a first insulating layer on the wall and bottom surface of said trench portion and extending outside the trench portion on the major surface of said substrate; said trench portion being filled in the inside thereof with a material of a first conductivity type up to the depth of said first insulating layer; a first single crystal silicon layer formed on said first insulating layer; diffusion regions in said first single crystal silicon layer serving as source and drain regions formed on said first insulating layer and said material of the first conductivity type by doping said first single crystal silicon layer with a first impurity to a high degree of concentration; a second insulating layer formed on said first single crystal silicon layer; a low resistive portion serving as a source or drain region formed on said second insulating layer; a second single crystal silicon layer formed along inner surfaces of said second insulating layer and said low resistive portion; a gate insulating layer formed on said low resistive portion and along said surface of said second single crystal silicon layer and said diffused region and having a trench portion on said material of a first conductivity type; and a gate electrode formed by filling a material of a first conductivity type in the trench portion of said gate insulating layer above the trench portion of said substrate; said low resistive portion being electrically coupled to a bit line and said gate electrode being connected to a word line.