US5170372A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory device having bit lines over a field oxide
Assignee: Texas Instruments Inc
•
Filing: 1992-04-15
•
Granted: 1992-12-08
•
Expires: 2012-04-15
Abstract
Abstract A memory device having an array of memory cells each including a trench capacitor and a pass transistor. The transistor has its source connected to the storage capacitor, its drain connected to a bit line, and its gate connected to a word line. The bit line is formed over a field oxide layer formed on the semiconductor substrate so there is minimal contact between the bit line and the semiconductor substrate. The storage dielectric in the trench is recessed from the surface of the semiconductor substrate.
Inventors
- 👤 Man Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:17
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
152 words
A memory cell in a semiconductor substrate comprising: a field oxide layer on the surface of said substrate, said field oxide layer patterned to selectively expose a surface of said semiconductor substrate and including a region defined by edges; a capacitor having a capacitor plate material therein for storage of electrical charge within said capacitor; a pass gate transistor having a source and a drain, the drain of said transistor operably connected to said capacitor so as to transfer signals between said capacitor and a bit line; and said bit line covering said region of said field oxide layer, said bit line extending sufficiently beyond said edges of said region such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of said pass gate transistor, and whereby said bit line has substantially no other contact with said substrate.
Claim 2
Dependent Claim
152 words
A memory cell in a semiconductor substrate comprising: a field oxide layer on the surface of said substrate, said field oxide layer patterned to selectively expose a surface of said semiconductor substrate and including a region defined by edges; a capacitor having a capacitor plate material therein for storage of electrical charge within said capacitor; a pass gate transistor having a source and a drain, the drain of said transistor operably connected to said capacitor so as to transfer signals between said capacitor and a bit line; and said bit line covering said region of said field oxide layer, said bit line extending sufficiently beyond said edges of said region such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of said pass gate transistor, and whereby said bit line has substantially no other contact with said substrate.
Claim 3
Dependent Claim
21 words
The memory cell as defined in claim 1, wherein said capacitor plate material is recessed from the surface of said substrate.
Claim 4
Dependent Claim
25 words
The memory cell as defined in claim 1, further comprising a conductive layer connecting said capacitor plate and the drain of said pass gate transistor.
Claim 5
Dependent Claim
21 words
The memory cell as defined in claim 3, wherein said capacitor plate material is recessed from the surface of said substrate.
Claim 6
Dependent Claim
15 words
The memory cell as defined in claim 1, wherein said capacitor is a trench capacitor.
Claim 7
Dependent Claim
186 words
A memory device comprising: a semiconductor substrate; a field oxide layer on the surface of said semiconductor substrate, said field oxide layer patterned to selectively expose the surface of said semiconductor substrate and including a plurality of regions defined by edges; a plurality of trench capacitors formed in said substrate, each of said trenches having a capacitor plate material therein for storing charge within said trench; a plurality of pass gate transistors each having a source and drain, the drain of said transistors operably connected to an associated one of said trench capacitors so as to transfer signals between a selected one of said trench capacitors and an associated bit line, a bit line covering said plurality of regions of said field oxide layer, said bit line having a size selected to extend sufficiently beyond said edges of said regions such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of its associated one of said pass gate transistors, and whereby said bit line has substantially no other contact with said substrate.
Claim 8
Dependent Claim
186 words
A memory device comprising: a semiconductor substrate; a field oxide layer on the surface of said semiconductor substrate, said field oxide layer patterned to selectively expose the surface of said semiconductor substrate and including a plurality of regions defined by edges; a plurality of trench capacitors formed in said substrate, each of said trenches having a capacitor plate material therein for storing charge within said trench; a plurality of pass gate transistors each having a source and drain, the drain of said transistors operably connected to an associated one of said trench capacitors so as to transfer signals between a selected one of said trench capacitors and an associated bit line, a bit line covering said plurality of regions of said field oxide layer, said bit line having a size selected to extend sufficiently beyond said edges of said regions such that said bit line contacts the surface of said substrate only at said edges, said bit line being connected to the source region of its associated one of said pass gate transistors, and whereby said bit line has substantially no other contact with said substrate.
Claim 9
Dependent Claim
21 words
The memory device as defined in claim 6, wherein said capacitor plate material is recessed from the surface of said substrate.
Claim 10
Dependent Claim
30 words
The memory cell as defined in claim 6, further comprising a conductive layer connecting said capacitor plate material and the drain of its associated one of said pass gate transistors.
Claim 11
Dependent Claim
21 words
The memory cell as defined in claim 8, wherein said capacitor plate material is recessed from the surface of said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |