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US5170226A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabrication of quantum devices in compound semiconductor layers and resulting structures

Assignee: International Business Machines Corp
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Filing: 1991-05-17
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Granted: 1992-12-08
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Expires: 2011-05-17
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Abstract

Abstract Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted. A wire-like shape free of As microcrystals then acts as a quantum wire for electrons or holes whereas a dot-like shape free of As microcrystals acts as a quantum dot. The co-existence of Ga ions and dopant ions, which provides conductivity type carriers opposite to the conductivity type of the majority carriers of a channel region of an FET, provides the fabrication of very narrow junction gate region for any FET.

Inventors

  • 👤 Tadashi Fukuzawa
  • 👤 Hiro Munekata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 11:37
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; B; B82; B82Y; B82Y10/00; H10D; H10D30/00; H10D30/01; H10D30/014; H10D30/051; H10P14/00; H10P14/20; H10P14/38; H10P14/3824; H10P30/208; H10W; H10W90/00; H10D62/00; H10D62/80; H10D62/85; H10W90/20; H10W90/297; Y; Y10; Y10S; Y10S438/00; Y10S438/962

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 57 words
An electronic structure comprising: at least one compound semiconductor layer containing clusters of one of the compound semiconductor elements of said layer which render said layer resistive, and at least a discrete region disposed in said at least one layer said region being a region of said compound semiconductor substantially free of said clusters and electrically conductive.
Claim 2
Dependent Claim 57 words
An electronic structure comprising: at least one compound semiconductor layer containing clusters of one of the compound semiconductor elements of said layer which render said layer resistive, and at least a discrete region disposed in said at least one layer said region being a region of said compound semiconductor substantially free of said clusters and electrically conductive.
Claim 3
Dependent Claim 26 words
An electronic structure according to claim 1 wherein said compound semiconductor is one taken from Groups III and V of the Periodic Table of the Elements.
Claim 4
Dependent Claim 26 words
An electronic structure according to claim 1 wherein said compound semiconductor is one taken from Groups II and VI of the Periodic Table of the Elements.
Claim 5
Dependent Claim 27 words
An electronic structure according to claim 1 wherein said one of said elements is an element taken from Group V of the Periodic Table of the Elements.
Claim 6
Dependent Claim 27 words
An electronic structure according to claim 1 wherein said one of said elements is an element taken from Group VI of the Periodic Table of the Elements.
Claim 7
Dependent Claim 28 words
An electronic structure according to claim 1 further including an isolation layer disposed over said at least one layer and a cap layer disposed over said isolation layer.
Claim 8
Dependent Claim 22 words
An electronic structure according to claim 1 wherein said compound semiconductor is gallium arsenide and said one of said elements is arsenic.
Claim 9
Dependent Claim 22 words
An electronic structure according to claim 1 wherein said compound semiconductor is zinc selenide and said one of said elements is selenium.
Claim 10
Dependent Claim 22 words
An electronic structure according to claim 1 wherein said at least one compound semiconductor layer is doped with a conductivity-type determining impurity.
Claim 11
Dependent Claim 21 words
An electronic structure according to claim 1 wherein said at least a discrete region is doped with a conductivity-type determining impurity.
Claim 12
Dependent Claim 17 words
An electronic structure according to claim 1 wherein said at least a region is a quantum wire.
Claim 13
Dependent Claim 17 words
An electronic structure according to claim 1 wherein said at least a region is a quantum dot.
Claim 14
Dependent Claim 31 words
An electronic structure according to claim 6 further including contact means extending from the surface of said cap layer through said isolation layer and contacting said at least a discrete region.
Claim 15
Dependent Claim 19 words
An electronic structure according to claim 6 wherein said isolation layer and said cap layer are compound semiconductor layers.
Claim 16
Dependent Claim 31 words
An electronic structure according to claim 13 wherein said contact means are comprised of a conductivity-type determining impurity in regions of said compound semiconductor which are substantially free of said clusters.
Claim 17
Dependent Claim 43 words
A semiconductor device comprising, a semiconductor substrate, a III-V compound semiconductor layer in which clusters of a Group V element embedded in said layer substantially deplete said layer of carriers, and at least one discrete region disposed in said layer which is undepleted.
Claim 18
Dependent Claim 43 words
A semiconductor device comprising, a semiconductor substrate, a III-V compound semiconductor layer in which clusters of a Group V element embedded in said layer substantially deplete said layer of carriers, and at least one discrete region disposed in said layer which is undepleted.

References Cited (Backward Citations)

US4960718A Cited
US4748132A Cited
US4876218A Cited
US5113072A Cited
US5051786A Cited
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US5084743A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-12-08 1996-06-08 1996-12-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-12-08 2000-06-08 2000-12-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-12-08 2004-06-08 2004-12-08 $7700.00 Window Closed / Lapsed

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