US4960718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MESFET device having a semiconductor surface barrier layer
Assignee: Honeywell International Inc
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Filing: 1988-07-05
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Granted: 1990-10-02
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Expires: 2008-07-05
Abstract
Abstract An InP MESFET having a semiconductor surface barrier layer formed of GaInP or AlInP. The semiconductor surface barrier layer is formed between an active layer and a gate electrode and the barrier height of the gate for the semiconductor surface barrier layer is higher than the barrier height of the gate for InP. In a method of forming an InP MESFET according to the present invention, the semiconductor surface barrier layer is formed by high dose implantation of Ga or Al into the active region. Surface barrier layers formed of other compounds, for example GaInAsP or AlInAsP, which have a lattice match with InP can be formed by other methods such as epitaxial growth.
Inventors
- 👤 Olaleye A. Aina
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:09
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D64/00; H10D64/60; H10D64/64; H10P30/202; H10P30/206; H10P30/208; H10P30/218; H10P30/28; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/646; H10W; H10W10/00; H10W10/01; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
144 words
A method of fabricating a semiconductor device on a semi-insulating InP substrate, comprising the steps of: (a) forming an active layer in the InP substrate; (b) forming a semiconductor surface barrier layer in the active layer by implanting an element selected from the group of Ga and Al; (c) forming a gate electrode on a portion of the semiconductor surface barrier layer, the barrier height across the interface of the gate electrode and the semiconductor surface barrier layer being higher than the barrier height across an interface of the gate electrode and the active region; (d) removing selected portions of the semiconductor surface barrier layer; (e) forming source and drain regions on selected portions of the surface of the active layer where the semiconductor surface barrier layer has been removed; and (f) annealing the semiconductor device at a temperature of at least 700° C.
Claim 2
Independent Claim
144 words
A method of fabricating a semiconductor device on a semi-insulating InP substrate, comprising the steps of: (a) forming an active layer in the InP substrate; (b) forming a semiconductor surface barrier layer in the active layer by implanting an element selected from the group of Ga and Al; (c) forming a gate electrode on a portion of the semiconductor surface barrier layer, the barrier height across the interface of the gate electrode and the semiconductor surface barrier layer being higher than the barrier height across an interface of the gate electrode and the active region; (d) removing selected portions of the semiconductor surface barrier layer; (e) forming source and drain regions on selected portions of the surface of the active layer where the semiconductor surface barrier layer has been removed; and (f) annealing the semiconductor device at a temperature of at least 700° C.
Claim 3
Dependent Claim
23 words
A method according to claim 1, further comprising the step of forming source and drain electrodes on the respective source and drain regions.
Claim 4
Dependent Claim
46 words
A method according to claim 1, wherein: step (a) comprises implanting Si at approximately 125 keV with a dose of approximately 5×10 12 cm -2 ; and step (e) comprises implanting Si at approximately 50 keV with a dose of approximately 10 - cm -1 .
Claim 5
Dependent Claim
20 words
A method according to claim 1, further comprising the step of forming isolation regions to electrically isolate the semiconductor device.
Claim 6
Dependent Claim
28 words
A method according to claim 4, wherein said isolation region forming step comprises implanting ions of an element selected from the group of Fe and O 2 .
Claim 7
Dependent Claim
27 words
A method according to claim 1, wherein step (d) comprises etching the selected portions of the semiconductor surface barrier layer using the gate electrode as a mask.
Claim 8
Dependent Claim
19 words
A method according to claim 1, wherein step (f) comprises annealing at approximately 850° C. for approximately 15 minutes.
Claim 9
Dependent Claim
27 words
A method according to claim 1, wherein: step (b) comprises implanting at approximately 25 keV with a dose of 2×10 16 to 2×10 17 cm -2 .
Claim 10
Dependent Claim
24 words
A method according to claim 1, wherein: step (b) comprises implanting at approximately 60 keV with a dose of 2×10 16 cm -2 .
Claim 11
Dependent Claim
20 words
A method according to claim 1, wherein: step (b) forms a surface barrier layer having a thickness of approximately 600A.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-10-01 | 1994-04-02 | 1994-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-01 | 1998-04-02 | 1998-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-01 | 2002-04-02 | 2002-10-02 | $7700.00 | Window Closed / Lapsed |