US5166557A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate array with built-in programming circuitry
Assignee: Texas Instruments Inc
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Filing: 1991-01-02
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Granted: 1992-11-24
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Expires: 2011-01-02
Abstract
Abstract A field programmable gate array having anti-fuse crosspoints. The input and output circuits of the gate array are especially designed so that the low voltage logic modules are not affected by high programming voltages. Each logic module is designed to be part of the programming circuit, rather than being isolated from it.
Inventors
- 👤 Kueing-Long Chen
- 👤 David K. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:58
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/1778; H03K19/17704; H03K19/17724; H03K19/17728
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
79 words
A logic module for a field programmable gate array having anti-fuse crosspoints, comprising: an output circuit configured as a pull-up circuit having two N-channel metal oxide silicon transistors, wherein said output circuit has at least one connection point for connecting said n-channel transistors to anti-fuse crosspoints; and an input circuit having two high voltage transistors in a totem pole configuration, wherein said input circuit has at least one connection point for connecting said high voltage transistors to anti-fuse crosspoints.
Claim 2
Dependent Claim
79 words
A logic module for a field programmable gate array having anti-fuse crosspoints, comprising: an output circuit configured as a pull-up circuit having two N-channel metal oxide silicon transistors, wherein said output circuit has at least one connection point for connecting said n-channel transistors to anti-fuse crosspoints; and an input circuit having two high voltage transistors in a totem pole configuration, wherein said input circuit has at least one connection point for connecting said high voltage transistors to anti-fuse crosspoints.
Claim 3
Dependent Claim
15 words
The logic module of claim 1, wherein said input circuit transistors are thick oxide transistors.
Claim 4
Dependent Claim
31 words
The logic module of claim 1, wherein said output circuit and said input circuit are capable of receiving a programming voltage of approximately twice the operational voltage at said connection points.
Claim 5
Dependent Claim
23 words
The logic module of claim 3, wherein said programming voltage is less than the breakdown voltage of said transistors of said output circuit.
Claim 6
Dependent Claim
105 words
A field programmable gate array, comprising: a number of logic modules, each logic module having an output circuit configured as a pull-up circuit having two N-channel metal oxide silicon transistors, wherein said output circuit has at least one connection point for connecting said N-channel transistors to anti-fuse crosspoints, and each logic module having an input circuit having tow high voltage transistors in a totem pole configuration, wherein said input circuit has at least one connection point for connecting said high voltage transistors to anti-fuse crosspoints; an array of anti-fuse crosspoints; and a matrix of interconnection lines for connecting said logic modules via said anti-fuse crosspoints.
Claim 7
Dependent Claim
105 words
A field programmable gate array, comprising: a number of logic modules, each logic module having an output circuit configured as a pull-up circuit having two N-channel metal oxide silicon transistors, wherein said output circuit has at least one connection point for connecting said N-channel transistors to anti-fuse crosspoints, and each logic module having an input circuit having tow high voltage transistors in a totem pole configuration, wherein said input circuit has at least one connection point for connecting said high voltage transistors to anti-fuse crosspoints; an array of anti-fuse crosspoints; and a matrix of interconnection lines for connecting said logic modules via said anti-fuse crosspoints.
Claim 8
Dependent Claim
20 words
The gate array of claim 5, and further comprising a programming switch for switching between a programming voltage and ground.
Claim 9
Dependent Claim
15 words
The logic module of claim 5, wherein said input circuit transistors are thick oxide transistors.
Claim 10
Dependent Claim
31 words
The logic module of claim 5, wherein said output circuit and said input circuit are capable of receiving a programming voltage of approximately twice the operational voltage at said connecting points.
Claim 11
Dependent Claim
23 words
The logic module of claim 8, wherein said programming voltage is less than the breakdown voltage of said transistors of said output circuit.
Claim 12
Independent Claim
87 words
A method of programming a field programmable gate array, comprising the steps of: connecting logic module outputs to anti-fuse crosspoints, using a pull-up circuit having two N channel metal-oxide-silicon transistors at the output node; connecting logic module inputs to anti-fuse crosspoints, using a two-transistor totem pole circuit having two high-voltage transistors at the input node; and interconnecting said logic modules by applying a programming voltage across a selected one of said anti-fuse crosspoints, wherein said programming voltage is also across said output node and said input node.
Claim 13
Independent Claim
87 words
A method of programming a field programmable gate array, comprising the steps of: connecting logic module outputs to anti-fuse crosspoints, using a pull-up circuit having two N channel metal-oxide-silicon transistors at the output node; connecting logic module inputs to anti-fuse crosspoints, using a two-transistor totem pole circuit having two high-voltage transistors at the input node; and interconnecting said logic modules by applying a programming voltage across a selected one of said anti-fuse crosspoints, wherein said programming voltage is also across said output node and said input node.
Claim 14
Dependent Claim
19 words
The method of claim 10, wherein said programming voltage is approximately twice the operational voltage of said logic modules.
Claim 15
Dependent Claim
24 words
The method of claim 10, wherein said programming voltage is less than the breakdown voltage of said N channel transistors of said output circuit.
Claim 16
Dependent Claim
33 words
The method of claim 10, wherein said step of applying a programming voltage comprises tri-stating said transistors of said output circuit and making a connection to ground on one side of said crosspoint.
Claim 17
Dependent Claim
47 words
The method of claim 10, wherein said step of applying a programming voltage comprises switching said transistors of said output circuit, using a control signal, such that one transistor is off and one is on, thereby making a connection to ground on one said of said crosspoint.
Claim 18
Dependent Claim
36 words
The method of claim 10, wherein said step of applying a programming voltage comprises connecting one side of said crosspoint to ground such that said programming voltage is across said crosspoint and at said input node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |