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US4785199A Expired / Lapsed US ⏱️ 0.0 years remaining

Programmable complementary transistors

Assignee: Zoran Corp
•
Filing: 1986-09-22
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Granted: 1988-11-15
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Expires: 2006-09-22
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Abstract

Abstract Programmable logic gate structures employ pairs of complementary transistors. Programming of the transistors is accomplished either by voltage biasing a shared floating gate of a CMOS transistor pair or by providing a variable resistance serially or in parallel with each transistor. The variable resistance can be a fusible link or a semiconductor device having an alterable crystalline structure.

Inventors

  • 👤 Avinoam Kolodny
  • 👤 Yigal Brandman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 20:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 210 words
A logic gate comprising a first field effect transistor and a first variable resistance device connected in parallel, a second field effect transistor and a second variable resistance device connected in parallel, a third field effect transistor and a third variable resistance device serially connected, a fourth field effect transistor and a fourth variable resistance device serially connected, means connecting said third field effect transistor and said third variable resistance in parallel with said fourth field effect transistor and said fourth variable resistance thereby forming parallel circuitry, means serially connecting said first field effect transistor, said second field effect transistor, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, said first and second field effect transistors being complementary, means for applying a second input to said second and fourth field effect transistors, said second and fourth transistors being complementary, and means for obtaining an output at the connection between said second field effect transistor and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input.
Claim 2
Dependent Claim 210 words
A logic gate comprising a first field effect transistor and a first variable resistance device connected in parallel, a second field effect transistor and a second variable resistance device connected in parallel, a third field effect transistor and a third variable resistance device serially connected, a fourth field effect transistor and a fourth variable resistance device serially connected, means connecting said third field effect transistor and said third variable resistance in parallel with said fourth field effect transistor and said fourth variable resistance thereby forming parallel circuitry, means serially connecting said first field effect transistor, said second field effect transistor, and said parallel circuitry between first and second voltage potentials, means for applying a first input to said first and third field effect transistors, said first and second field effect transistors being complementary, means for applying a second input to said second and fourth field effect transistors, said second and fourth transistors being complementary, and means for obtaining an output at the connection between said second field effect transistor and said parallel circuitry in response to said first and second inputs, said first, second, third, and fourth variable resistance devices having a high resistance state and a low resistance state for selectively enabling said first input and said second input.
Claim 3
Dependent Claim 15 words
The logic gate as defined by claim 1 wherein said resistance devices comprise fusible links.
Claim 4
Dependent Claim 17 words
The logic gate as defined by claim 1 wherein said resistance devices comprise doped polycrystalline semiconductor material.

References Cited (Backward Citations)

SU399916A1 Cited
US4016588A Cited
US4148044A Cited
JPS5478679A Cited
US4228527A Cited
US4302766A Cited
JPS57882A Cited
US4402064A Cited
EP0103043A1 Cited
US4609830A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-11-15 1992-05-16 1992-11-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-11-15 1996-05-16 1996-11-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-11-15 2000-05-16 2000-11-15 $7700.00 Window Closed / Lapsed

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