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Patent US5161219A successfully refreshed from Google Patents.
US5161219A
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Computer system with input/output cache
Assignee: International Business Machines Corp
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Filing: 1991-05-31
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Granted: 1992-11-03
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Expires: 2011-05-31
Abstract
Abstract A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.
Inventors
- 👤 James O. Nicholson
- 👤 John C. O'Quin, III
- 👤 II John T. O'Quin
- 👤 Frederick E. Strietelmeier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:53
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/084; G06F12/0844; G06F12/0846; G06F12/0848
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
171 words
A computer system, comprising: central processor means for initiating system memory transactions; a system memory including a central processor non-shared region, an input/output non-shared region, and a shared region; central processor cache means, connected to said central processor means and to the system memory and responsive to system memory transactions initiated by the central processor means, for executing system memory transactions between the central processor means and the central processor non-shared region of said system memory and for caching all memory accesses to the central processor non-shared region; input/output means for initiating system memory transactions; and input/output cache means, connected to said input/output means, to the central processor means and to said system memory, and responsive to memory transactions initiated by the input/output means for executing all system memory transactions between the input/output means and the input/output non-shared region and the shared region, and further responsive to system memory transactions initiated by said central processor means for executing all system memory transactions between the central processing means and the shared region.
Claim 2
Dependent Claim
171 words
A computer system, comprising: central processor means for initiating system memory transactions; a system memory including a central processor non-shared region, an input/output non-shared region, and a shared region; central processor cache means, connected to said central processor means and to the system memory and responsive to system memory transactions initiated by the central processor means, for executing system memory transactions between the central processor means and the central processor non-shared region of said system memory and for caching all memory accesses to the central processor non-shared region; input/output means for initiating system memory transactions; and input/output cache means, connected to said input/output means, to the central processor means and to said system memory, and responsive to memory transactions initiated by the input/output means for executing all system memory transactions between the input/output means and the input/output non-shared region and the shared region, and further responsive to system memory transactions initiated by said central processor means for executing all system memory transactions between the central processing means and the shared region.
Claim 3
Dependent Claim
31 words
The computer system of claim 1, wherein said input/output cache means is further responsive to system memory transactions for caching data received by all memory accesses through said input/output cache means.
Claim 4
Dependent Claim
27 words
The computer system of claim 1, and further comprising bus means connected between said central processor means and said input/output means for directly executing data transactions therebetween.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |