US5156981A
Expired / Lapsed
US
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Method of making a semiconductor device of a high withstand voltage
Assignee: Toshiba Corp
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Filing: 1989-04-06
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Granted: 1992-10-20
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Expires: 2009-04-06
Abstract
Abstract Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.
Inventors
- 👤 Mitsuhiko Kitagawa
- 👤 Yoshio Yokota
- 👤 Kazuo Watanuki
- 👤 Yoshinari Uetake
- 👤 Kazunobu Nishitani
- 👤 Tsuneo Ogura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:20
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/01; H10D18/60; H10D62/00; H10D62/10; H10D62/117; H10D62/13; H10D62/141; H10D62/142; H10D62/60; H10D8/00; H10D8/50; H10W; H10W72/00; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/138
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
194 words
A method of manufacturing semiconductor devices of high withstand voltage, comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer and an impurity of phosphorus into a second major surface of said n-type base layer by an ion implanting method; a second step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a selected temperature; a third step of simultaneously diffusing both said impurities for a longer time and at a high temperature than those in said pre-drive-in diffusion, to thereby simultaneously form a p-type base layer in the first major surface of said n-type base layer and an n-type buffer layer in the second major surface of said n-type base layer; a fourth step of introducing, by using predetermined masks, an n-type impurity into the entire surface of said p-type base layer and a p-type impurity into the surface of said n-type buffer layer; and a fifth step of forming an n-type emitter layer in said p-type base layer and a p-type emitter layer in said n-type buffer layer, by diffusing each of the impurities included in said fourth step.
Claim 2
Independent Claim
194 words
A method of manufacturing semiconductor devices of high withstand voltage, comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer and an impurity of phosphorus into a second major surface of said n-type base layer by an ion implanting method; a second step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a selected temperature; a third step of simultaneously diffusing both said impurities for a longer time and at a high temperature than those in said pre-drive-in diffusion, to thereby simultaneously form a p-type base layer in the first major surface of said n-type base layer and an n-type buffer layer in the second major surface of said n-type base layer; a fourth step of introducing, by using predetermined masks, an n-type impurity into the entire surface of said p-type base layer and a p-type impurity into the surface of said n-type buffer layer; and a fifth step of forming an n-type emitter layer in said p-type base layer and a p-type emitter layer in said n-type buffer layer, by diffusing each of the impurities included in said fourth step.
Claim 3
Independent Claim
234 words
A method of manufacturing semiconductor devices of high withstand voltage, comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer and an impurity of phosphorus into a second major surface of said n-type base layer by an ion implanting method; a second step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a selected temperature; a third step of simultaneously diffusing both said impurities for a longer time at a higher temperature than those in said pre-drive-in diffusion, to thereby simultaneously form a p-type base layer in the first major surface of said n-type base layer and an n-type buffer layer in the second major surface of said n-type base layer; a fourth step of introducing, by using predetermined masks, an n-type impurity into the entire surface of said p-type base layer and a p-type impurity into a selected part of the surface of said n-type buffer layer; a fifth step of introducing an n-type impurity into the entire surface of said n-type buffer layer; and a sixth step of simultaneously forming an n-type emitter layer in said p-type base layer and a p-type emitter layer and an n-type anode short layer in said n-type buffer layer, by diffusing each of the impurities introduced in said fourth and fifth steps, said anode short layer being shallower than said p-type emitter layer.
Claim 4
Independent Claim
234 words
A method of manufacturing semiconductor devices of high withstand voltage, comprising: a first step of introducing an impurity of boron into a first major surface of an n-type base layer and an impurity of phosphorus into a second major surface of said n-type base layer by an ion implanting method; a second step of simultaneously pre-drive-in diffusing both of said impurities by heating them at a selected temperature; a third step of simultaneously diffusing both said impurities for a longer time at a higher temperature than those in said pre-drive-in diffusion, to thereby simultaneously form a p-type base layer in the first major surface of said n-type base layer and an n-type buffer layer in the second major surface of said n-type base layer; a fourth step of introducing, by using predetermined masks, an n-type impurity into the entire surface of said p-type base layer and a p-type impurity into a selected part of the surface of said n-type buffer layer; a fifth step of introducing an n-type impurity into the entire surface of said n-type buffer layer; and a sixth step of simultaneously forming an n-type emitter layer in said p-type base layer and a p-type emitter layer and an n-type anode short layer in said n-type buffer layer, by diffusing each of the impurities introduced in said fourth and fifth steps, said anode short layer being shallower than said p-type emitter layer.
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