Latching transistor

Claim 1

A semiconductor switching device of the four-vertically-superimposed-layer gate-turn-off type having controllable emitter shorting and adapted to be turned both on and off by gate signals comprising: a semiconductor body having first and second vertically separated and overlapping opposite major surfaces; a first emitter region of a first conductivity type in said first surface having two spaced comb-shaped sections each including a relatively wide spine from which extends longitudinally and parallel to said first major surface a set of relatively narrow fingers with the fingers of each set extending toward but being spaced from the fingers of the other set; first emitter electrode means on said first surface in ohmic contact with said first emitter region; a first base region of a second conductivity type adjacent said first emitter region and forming a first p-n junction therewith, said junction terminating on said first major surface; comb-shaped gate electrode means on said first major surface interdigitated with said first emitter region and in ohmic contact with said first base region, said gate electrode means being adjacent to but laterally spaced apart from said first p-n junction; a second base region of said first conductivity type adjacent and vertically beneath said first base region and forming a second p-n junction therewith; a control region of said first conductivity type adjacent and vertically beneath said second base region and spaced from the first base region by said second base region, said control region having a higher impurity concentration than said second base region; a selectively shorted second emitter region of said second conductivity type adjacent said control region in vertically underlying relation with said first emitter region; said second emitter region being situated in vertically underlying relation with essentially only that part of the first emitter region other than the spine portions of the first emitter region; said second emitter region including a central spine region vertically underlying essentially the space between the two sets of first emitter fingers and further including a plurality of spaced second emitter fingers extending from said central spine region in vertically underlying relation with essentially only a part of the first major surface not occupied by the spine portion of the first emitter; said second emitter fingers each including a projection extending from its end into vertical alignment with a spine portion of the first emitter region; said second emitter region further having longitudinally extending apertures therein constituted by the spaces between the second emitter fingers, which apertures are narrower than said first emitter fingers and vertically aligned with only the laterally central portions of said first emitter fingers; said control region extending through said apertures to said second major surface to form with said second emitter region a third p-n junction terminating on second major surface.