US4551744A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High switching speed semiconductor device containing graded killer impurity
Assignee: Hitachi Ltd
•
Filing: 1982-07-30
•
Granted: 1985-11-05
•
Expires: 2002-07-30
Abstract
Abstract A semiconductor device for controlling a current comprises a pn junction formed of a high resistivity region and a relatively low resistivity region, a graded distribution of dislocation density is formed in the high resistivity region and decreases with an increase in distance from the pn junction, also graded distribution of lifetime killer concentration is formed in the high resistivity region and decreases with an increase in distance from the pn junction in correspondence with the graded distribution of dislocation density.
Inventors
- 👤 Kensuke Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:28
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/834; H10D18/00; H10D18/241; H10D8/00; H10D8/422; H10P; H10P36/00; H10P36/03; H10P95/00; H10P95/40; H10P95/402
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A semiconductor device including at least one pn junction across which a current is allowed to flow, comprising: a first semiconductor region of a first conductivity type having a high resistivity; a second semiconductor region of a second conductivity type opposite to said first conductivity type, having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to said first semiconductor region to form one of said at least one pn junction therebetween; and a graded distribution of lifetime killer formed in substantially the whole portion of said first semiconductor region and having a killer concentration distribution which decreases with an increase in distance from said one pn junction.
Claim 2
Dependent Claim
113 words
A semiconductor device including at least one pn junction across which a current is allowed to flow, comprising: a first semiconductor region of a first conductivity type having a high resistivity; a second semiconductor region of a second conductivity type opposite to said first conductivity type, having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to said first semiconductor region to form one of said at least one pn junction therebetween; and a graded distribution of lifetime killer formed in substantially the whole portion of said first semiconductor region and having a killer concentration distribution which decreases with an increase in distance from said one pn junction.
Claim 3
Dependent Claim
44 words
A semiconductor device according to claim 1, further comprising: graded distribution of dislocation formed in said first semiconductor region for enhancing doping of said lifetime killer and having a dislocation density distribution which decreases with an increase in distance from said one pn junction.
Claim 4
Dependent Claim
79 words
A semiconductor device according to claim 2, further comprising: a third semiconductor region of said first conductivity type having a resistivity lower than that of said first semiconductor region and disposed adjacent to an end of said first semiconductor region opposite to said second semiconductor region; and said distributions of the lifetime killer concentration and the dislocation density decreasing with an increase in distance from said one pn junction in substantially a main part of said first semiconductor region.
Claim 5
Dependent Claim
87 words
A semiconductor device according to claim 2, further comprising: a third semiconductor region of said second conductivity type having an impurity concentration higher than that of said first semiconductor region and disposed adjacent to an end of said first semiconductor region opposite to said second semiconductor region to form another of said at least one pn junction therebetween; and said distributions of dislocation density and lifetime killer concentration decreasing in portions from said one and another pn junctions toward a central portion of the first semiconductor region.
Claim 6
Dependent Claim
37 words
A semiconductor device according to claim 3, wherein said first conductivity type is n type and said third semiconductor region is doped with phosphorus of a concentration higher than the impurity concentration of said second semiconductor region.
Claim 7
Dependent Claim
36 words
A semiconductor device according to any one of claims 1 to 5, wherein the impurity concentration of said second semiconductor region is at least two orders of magnitude higher than that of said first semiconductor region.
References Cited (Backward Citations)
US3067485A
Cited
US3440113A
Cited
US3487276A
Cited
US3485684A
Cited
GB1447763A
Cited
US4259683A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-04 | 1989-05-06 | 1989-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-04 | 1993-05-06 | 1993-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-04 | 1997-05-06 | 1997-11-05 | $7700.00 | Window Closed / Lapsed |