High switching speed P-N junction devices with recombination means centrally located in high resistivity layer

Claim 2

In a PIN semiconductor diode exhibiting first and second stages of turn-off and including a layer of P type semiconductor material, a layer of intrinsic semiconductor material I, and a layer of N-type semiconductor material in a sandwich-like relationship, a P-I junction being formed between said P-type layer and said I layer, and an I-N junction being formed between said I layer and said N-type layer, said P-type layer and said N-type layer each having an electrical contact for connecting said diode to external electrical circuitry, the improvement comprising: a region of reduced carrier lifetime situated within said intrinsic semiconductor layer including, and substantially limited to, the portion of the volume thereof in which the peak amount of carrier recombination occurs during the second stage of turn-off of said diode caused by changing a forward bias voltage applied to the electrical contacts of said diode to a reverse bias voltage, said region of reduced carrier lifetime oriented generally perpendicular to the flow of current through said diode and generally situated near the middle portion of said layer of intrinsic semiconductor material, said intrinsic semiconductor layer including a first region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said P-I junction, and a second region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said I-N junction, whereby carrier recombination during device turn-off is enhanced so as to result in decreased turn-off time.

Claim 3

The PIN semiconductor diode of claim 1 wherein said region of reduced carrier lifetime occupies less than 25% of the volume of said intrinsic semiconductor layer.

Claim 4

The PIN semiconductor diode of claim 2 wherein said region of reduced carrier lifetime exhibits a lifetime less than 60 percent of the lifetime of said intrinsic semiconductor layer.

Claim 5

In a transistor exhibiting first and second stages of turn-off, said transistor including a lightly doped collector region and a base region with a collector-base junction situated therebetween and including an emitter region with an emitter-base junction situated between said emitter and base regions, each of said collector, base and emitter regions having an electrical contact situated thereon to connect said device to external electrical circuitry, the turn-on and turn-off of the collector-to-emitter current of said transistor device being controlled by base current applied to said base electrical contact, the improvement comprising: a region of reduced carrier lifetime situated within said lightly doped collector region including, and substantially limited to, the portion of the volume thereof in which the peak amount of carrier recombination occurs during the second stage of turn-off of the collector-to-emitter current of said transistor, said region of reduced carrier lifetime oriented generally perpendicular to the flow of collector-to-emitter current through said device, and generally situated near the middle portion of said collector region, said collector region including a region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said collector-base junction, whereby carrier recombination during device turn-off is enhanced so as to result in decreased turn-off time.

Claim 6

In a transistor exhibiting first and second stages of turn-off, said transistor including a lightly doped collector region and a base region with a collector-base junction situated therebetween and including an emitter region with an emitter-base junction situated between said emitter and base regions, each of said collector, base and emitter regions having an electrical contact situated thereon to connect said device to external electrical circuitry, the turn-on and turn-off of the collector-to-emitter current of said transistor device being controlled by base current applied to said base electrical contact, the improvement comprising: a region of reduced carrier lifetime situated within said lightly doped collector region including, and substantially limited to, the portion of the volume thereof in which the peak amount of carrier recombination occurs during the second stage of turn-off of the collector-to-emitter current of said transistor, said region of reduced carrier lifetime oriented generally perpendicular to the flow of collector-to-emitter current through said device, and generally situated near the middle portion of said collector region, said collector region including a region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said collector-base junction, whereby carrier recombination during device turn-off is enhanced so as to result in decreased turn-off time.

Claim 7

The transistor device of claim 4 wherein said region of reduced carrier lifetime occupies less than 25% of the volume of said collector region.

Claim 8

The transistor device of claim 5 wherein said region of reduced carrier lifetime exhibits a carrier lifetime less than 60% of the lifetime of said collector region.

Claim 9

In a four-layer thyristor semiconductor device exhibiting first and second stages of turn-off and including a cathode layer, a first base layer, a lightly doped second base layer, and an anode layer of alternate conductivity types, and including first, second and third P-N junctions between said respective layers, said cathode, first base and anode layers each having an electrical contact for connecting said thyristor semiconductor device to external electrical circuitry, said thyristor semiconductor device adapted for electrical switching to provide a first relatively low resistance turned-on state and a second relatively high resistance turned-off voltage blocking state, the state of said semiconductor device being controlled by current applied to said first base layer, the improvement comprising: a region of reduced carrier lifetime situated within said lightly-doped second base layer including, and substantially limited to, the portion of the volume thereof in which the peak amount of carrier recombination occurs during the second stage of turn-off of said device, said region of reduced carrier lifetime oriented generally perpendicular to the flow of current from the cathode to the anode through said device, and generally situated near the middle portion of said second base layer, said second base layer including a first region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said second P-N junction, and a second region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said third P-N junction, whereby carrier recombination during device turn-off is enhanced so as to result in decreased turn-off time.

Claim 10

In a four-layer thyristor semiconductor device exhibiting first and second stages of turn-off and including a cathode layer, a first base layer, a lightly doped second base layer, and an anode layer of alternate conductivity types, and including first, second and third P-N junctions between said respective layers, said cathode, first base and anode layers each having an electrical contact for connecting said thyristor semiconductor device to external electrical circuitry, said thyristor semiconductor device adapted for electrical switching to provide a first relatively low resistance turned-on state and a second relatively high resistance turned-off voltage blocking state, the state of said semiconductor device being controlled by current applied to said first base layer, the improvement comprising: a region of reduced carrier lifetime situated within said lightly-doped second base layer including, and substantially limited to, the portion of the volume thereof in which the peak amount of carrier recombination occurs during the second stage of turn-off of said device, said region of reduced carrier lifetime oriented generally perpendicular to the flow of current from the cathode to the anode through said device, and generally situated near the middle portion of said second base layer, said second base layer including a first region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said second P-N junction, and a second region exhibiting a carrier recombination lifetime greater than that of said region of reduced carrier lifetime and situated between said region of reduced carrier lifetime and said third P-N junction, whereby carrier recombination during device turn-off is enhanced so as to result in decreased turn-off time.

Claim 11

The four layer thyristor semiconductor device of claim 7 wherein said region of reduced carrier lifetime occupies less than 25% of the volume of said second base layer.

Claim 12

The four layer thyristor semiconductor device of claim 8 wherein said region of reduced carrier lifetime exhibits a lifetime less than 60% of the lifetime of said second base layer.