US4236169A
Expired / Lapsed
US
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Thyristor device
Assignee: Hitachi Ltd
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Filing: 1979-06-19
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Granted: 1980-11-25
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Expires: 1999-06-19
Abstract
Abstract A semiconductor substrate comprises at the central portion a diode region which includes a P-type base layer, an N-type low impurity concentration layer and an N-type base layer and at the outer peripheral portion a thyristor region which includes an N-type emitter layer, a P-type base layer, an N-type low impurity concentration layer, an N-type base layer and a P-type emitter layer. The P-type base layer and the N-type emitter layer are in contact with a cathode electrode, the N-type base layer and the P-type emitter layer are in contact with an anode electrode, and the diode and thyristor regions are connected in anti-parallel. Contiguous to the outer periphery of the N-type base layer interposed between the N-type low impurity concentration layer and the P-type emitter layer is formed an N-type high impurity concentration region higher in impurity concentration than the N-type base layer. The N-type high impurity concentration region limits spreading of a depletion layer which is created when a forward voltage is applied to the thyristor region.
Inventors
- 👤 Yoichi Nakashima
- 👤 Yosikazu Takita
- 👤 Sousi Suzuki
- 👤 Katsumi Akabane
- 👤 Michihiro Misawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:24
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/241; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10D84/00; H10D84/101; H10D84/131; H10D84/135; H10D84/136
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
206 words
A thyristor comprising: a semiconductor substrate with a first major surface, a second major surface opposing said first major surface, and a side surface connecting said first and second major surfaces, said semiconductor substrate including a first emitter layer of one conductivity type contiguous to said first major surface, a second emitter layer of an opposite conductivity type contiguous to said second major surface, a first base layer of said opposite conductivity type contiguous to said first emitter layer, a second base layer of said one conductivity type contiguous to said second emitter layer, a low impurity concentration layer of said one conductivity type interposed between said first and second base layers and having an impurity concentration lower than that of said second base layer, and a high impurity concentration region of said one conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said side surface of said semiconductor substrate and having an impurity concentration higher than that of said second base layer; a cathode electrode in contact with said first emitter layer; an anode electrode in contact with said second emitter layer; and a gate electrode in contact with said first base layer.
Claim 2
Dependent Claim
206 words
A thyristor comprising: a semiconductor substrate with a first major surface, a second major surface opposing said first major surface, and a side surface connecting said first and second major surfaces, said semiconductor substrate including a first emitter layer of one conductivity type contiguous to said first major surface, a second emitter layer of an opposite conductivity type contiguous to said second major surface, a first base layer of said opposite conductivity type contiguous to said first emitter layer, a second base layer of said one conductivity type contiguous to said second emitter layer, a low impurity concentration layer of said one conductivity type interposed between said first and second base layers and having an impurity concentration lower than that of said second base layer, and a high impurity concentration region of said one conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said side surface of said semiconductor substrate and having an impurity concentration higher than that of said second base layer; a cathode electrode in contact with said first emitter layer; an anode electrode in contact with said second emitter layer; and a gate electrode in contact with said first base layer.
Claim 3
Dependent Claim
25 words
A thyristor according to claim 1, wherein said side surface of said semiconductor substrate is subjected to positive bevelling at least said second base layer.
Claim 4
Dependent Claim
358 words
A thyristor comprising: a semiconductor substrate with a first major surface, a second major surface opposing said first major surface, and a side surface connecting said first and second major surfaces, said semiconductor substrate including a first base layer of one conductivity type contiguous to said first major surface, a second base layer of an opposite conductivity type contiguous to said second major surface, a first emitter layer of said opposite conductivity type contiguous, on one hand, to the outer periphery of said first base layer and on the other hand, to said first major surface, said first emitter layer being cooperative with said first base layer to form a PN junction, a second emitter layer of said one conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said second major surface and said side surface, said second emitter layer being cooperative with said second base layer to form a PN junction, a low impurity concentration layer of said opposite conductivity type interposed between said first and second base layers and having an impurity concentration lower than that of said second base layer, and a high impurity concentration region of said opposite conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said side surface of said semiconductor substrate and having an impurity concentration higher than that of said second base layer; a cathode electrode in contact with said first emitter layer and said first base layer; an anode electrode in contact with said second emitter layer and said second base layer; and a gate electrode in contact with said first base layer, whereby said first base layer, said low impurity concentration layer and said second base layer form a diode region at the central portion of said semiconductor substrate while said first emitter layer, said first base layer, said low impurity concentration layer, said second base layer and said second emitter layer form a thyristor region at the outer peripheral portion of said semiconductor substrate, said diode and thyristor regions being connected in anti-parallel.
Claim 5
Dependent Claim
358 words
A thyristor comprising: a semiconductor substrate with a first major surface, a second major surface opposing said first major surface, and a side surface connecting said first and second major surfaces, said semiconductor substrate including a first base layer of one conductivity type contiguous to said first major surface, a second base layer of an opposite conductivity type contiguous to said second major surface, a first emitter layer of said opposite conductivity type contiguous, on one hand, to the outer periphery of said first base layer and on the other hand, to said first major surface, said first emitter layer being cooperative with said first base layer to form a PN junction, a second emitter layer of said one conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said second major surface and said side surface, said second emitter layer being cooperative with said second base layer to form a PN junction, a low impurity concentration layer of said opposite conductivity type interposed between said first and second base layers and having an impurity concentration lower than that of said second base layer, and a high impurity concentration region of said opposite conductivity type contiguous, on one hand, to the outer periphery of said second base layer and on the other hand, to said side surface of said semiconductor substrate and having an impurity concentration higher than that of said second base layer; a cathode electrode in contact with said first emitter layer and said first base layer; an anode electrode in contact with said second emitter layer and said second base layer; and a gate electrode in contact with said first base layer, whereby said first base layer, said low impurity concentration layer and said second base layer form a diode region at the central portion of said semiconductor substrate while said first emitter layer, said first base layer, said low impurity concentration layer, said second base layer and said second emitter layer form a thyristor region at the outer peripheral portion of said semiconductor substrate, said diode and thyristor regions being connected in anti-parallel.
Claim 6
Dependent Claim
33 words
A thyristor according to claim 3, wherein said high impurity concentration region is formed outside a region originating from projecting said first emitter layer upon the current flow path in said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-25 | 1984-05-26 | 1984-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-25 | 1988-05-26 | 1988-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-25 | 1992-05-26 | 1992-11-25 | $7700.00 | Window Closed / Lapsed |