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Patent US5155745A successfully refreshed from Google Patents.
US5155745A
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Synchronizer for asynchronous computer command data
Assignee: RPX Corp
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Filing: 1990-10-12
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Granted: 1992-10-13
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Expires: 2010-10-12
Abstract
Abstract Asynchronous command data are converted to synchronous data by a synchronizer comprising a toggle flip-flop which receives the asynchronous command data to produce a pair of true and complementary outputs in response to a transition of the command data. A first NOR gate is responsive to the command pulses and the true output of the toggle flip-flop to produce a train of first pulses, and a second NOR gate is responsive to the command pulses and the complementary output of toggle flip-flop to produce a train of second pulses. First and second sampling flip-flops are connected to the outputs of the first and second NOR gates, respectively, to sample the first and second pulses therefrom in response to a trailing edge transition of a clock signal with a frequency twice as high as the nominal maximum frequency of the command pulses. The output signals of the first and second sampling flip-flops are sampled in response to a leading edge transition of the clock signal and the sampled output signals are combined to produce a train of output pulses having transitions coinciding with transitions of the clock signal.
Inventors
- 👤 Akihiko Sugawara
- 👤 Yutaka Gotou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:00
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/24; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; H04L7/00; H04L7/02
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
A synchronizer comprising: a toggle flip-flop for receiving asynchronous input pulses and changing state of the flip-flop in response to a transition point of said received asynchronous input pulses to produce a pair of true and complementary outputs; gate means for receiving said asynchronous input pulses and said true and complementary outputs of said toggle flip-flop to produce a first train of pulses and a second train of pulses which alternate with those of said first train; first sampling flip-flop for sampling the pulses of said first train in response to a trailing edge transition of a clock signal with a frequency twice as high as nominal maximum frequency of said asynchronous input pulses; second sampling flip-flop for sampling the pulses of said second train in response to the trailing edge transition of said clock signal; and means for sampling output signals of said first and second sampling flip-flops in response to a leading edge transition of said clock signal and combining the sampled output signals to produce a train of output pulses having transitions coinciding with the leading edge transitions of said clock signal.
Claim 2
Dependent Claim
185 words
A synchronizer comprising: a toggle flip-flop for receiving asynchronous input pulses and changing state of the flip-flop in response to a transition point of said received asynchronous input pulses to produce a pair of true and complementary outputs; gate means for receiving said asynchronous input pulses and said true and complementary outputs of said toggle flip-flop to produce a first train of pulses and a second train of pulses which alternate with those of said first train; first sampling flip-flop for sampling the pulses of said first train in response to a trailing edge transition of a clock signal with a frequency twice as high as nominal maximum frequency of said asynchronous input pulses; second sampling flip-flop for sampling the pulses of said second train in response to the trailing edge transition of said clock signal; and means for sampling output signals of said first and second sampling flip-flops in response to a leading edge transition of said clock signal and combining the sampled output signals to produce a train of output pulses having transitions coinciding with the leading edge transitions of said clock signal.
Claim 3
Dependent Claim
23 words
A synchronizer as claimed in claim 1, wherein said asynchronous input pulses constitute an asynchronous computer command signal having active and inactive states.
Claim 4
Dependent Claim
152 words
A synchronizer as claimed in claim 2, wherein said sampling means comprises: a first set of flip-flops connected in series to said first sampling flip-flop, the flip-flops of said first set being responsive to a leading edge transition of said clock signal; a first coincidence gate connected to the flip-flops of said first set for producing a first output pulse which occurs during an active state of said asynchronous command signal; a second set of flip-flops connected in series to said second sampling flip-flop, the flip-flops of said second set being responsive to the leading edge transition of said clock signal; a second coincidence gate connected to the flip-flops of said second set for producing a second output pulse which occurs during an active state of said asynchronous command signal which occurs subsequent to said first output pulse; and means for combining the output pulses of said first and second coincidence gates.
Claim 5
Dependent Claim
45 words
A synchronizer as claimed in claim 3, further comprising means responsive to the flip-flops of said first and second sets for generating an asynchronous wait request signal and applying said asynchronous wait request signal to a source from which said asynchronous command signal is supplied.
Claim 6
Dependent Claim
33 words
A synchronizer as claimed in claim 4, further comprising means for generating a synchronous wait request signal and applying said synchronous wait request signal to the flip-flops of said first and second sets.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |