Data sampling architecture

Claim 2

A circuit for converting incoming asynchronous pulses to synchronous pulses of constant pulse width comprising: a first clock signal having rising edges; a second clock signal having falling edges; an input means receiving the incoming pulse and having first complementary output signals toggles in response to the asynchronous pulse; a synchronizer means including a first means for capturing the complementary output signals responsive to the rising edge of the first clock and providing first intermediate outputs responsive to the falling edge of the second clock and producing second intermediate outputs; third means for capturing the second intermediate output responsive to the falling edge of the second clock and providing inverted third intermediate outputs; means for combining the second and third intermediate outputs in a logical AND to produce fourth intermediate outputs; and means for combining the fourth intermediate outputs in a logical OR to provide a synchronized output.

Claim 3

A circuit as defined in claim 1 for use in a controller having a system clock wherein the first clock signal has twice the frequency of the system clock and the second clock signal has substantially the same frequency as the first clock signal but phase-shifted to lag the first clock signal, and wherein the first capturing means is responsive to the rising edge of the first clock signal, the second capturing means and third capturing means are responsive to the falling edge of the second clock signal.

Claim 4

A circuit for converting incoming asynchronous pulses to synchronous pulses of constant pulse width comprising: a first clock signal having leading and trailing edges; a second clock signal having leading and trailing edges; a first toggling flip-flop receiving the asynchronous pulses on a clock input and having a first inverting output and second non-inverting output, a second flip-flop responsive to the leading edge of the first clock signal and connected to the non-inverting output of the first flip-flop, the second flip-flop providing a first intermediate output signal; a third flip-flop responsive to the leading edge of the first clock signal, and connected to the inverting output of the first flip-flop, the third flip-flop providing a second intermediate output signal; a fourth flip-flop responsive to the trailing edge of the second clock signal, receiving the first intermediate output and providing a third intermediate output; a fifth flip-flop responsive to the trailing edge of the second clock signal, receiving the second intermediate output and providing a fourth intermediate output; a sixth flip-flop responsive to the trailing edge of the second clock signal, receiving the third intermediate output and providing a fifth intermediate output; a seventh flip-flop responsive to the trailing edge of the second clock signal, receiving the fourth intermediate output and providing a sixth intermediate output; a first AND gate receiving the third intermediate output and the fifth intermediate output; a second AND gate receiving the fourth intermediate output and the sixth intermediate output; and an OR gate connected to the first and second AND gates, the OR gate providing a system output.

Claim 5

A circuit for converting incoming asynchronous pulses to synchronous pulses of constant pulse width comprising: a first clock signal having leading and trailing edges; a second clock signal having leading and trailing edges; a first toggling flip-flop receiving the asynchronous pulses on a clock input and having a first inverting output and second non-inverting output, a second flip-flop responsive to the leading edge of the first clock signal and connected to the non-inverting output of the first flip-flop, the second flip-flop providing a first intermediate output signal; a third flip-flop responsive to the leading edge of the first clock signal, and connected to the inverting output of the first flip-flop, the third flip-flop providing a second intermediate output signal; a fourth flip-flop responsive to the trailing edge of the second clock signal, receiving the first intermediate output and providing a third intermediate output; a fifth flip-flop responsive to the trailing edge of the second clock signal, receiving the second intermediate output and providing a fourth intermediate output; a sixth flip-flop responsive to the trailing edge of the second clock signal, receiving the third intermediate output and providing a fifth intermediate output; a seventh flip-flop responsive to the trailing edge of the second clock signal, receiving the fourth intermediate output and providing a sixth intermediate output; a first AND gate receiving the third intermediate output and the fifth intermediate output; a second AND gate receiving the fourth intermediate output and the sixth intermediate output; and an OR gate connected to the first and second AND gates, the OR gate providing a system output.