Method and apparatus for producing successive calculated results in a high-speed computer functional unit using low-speed VLSI components

Claim 1

A multipath functional unit for a computer operative for producing successive calculated results at the frequency of the system clock of the computer, comprising: a system clock having a fixed frequency and having a single phase; n path clocks each having a frequency which is equal to the frequency of the system clock of the computer divided by n and each path clock having a different phase; n substantially identical data processing paths within a single functional unit for performing operations on operands applied thereto, wherein each data processing path comprises: at least one purely combinational logic block having a propogation delay greater than the period of the system clock; at least one input data latch connected to said purely combinational logic block and which is clocked by one of said path clocks; at least on output data latch connected to said purely combinational logic block and which is clocked by the same path clock which clocks said input data latch; data input means connected to the input data latch of each of said n plurality of substantially identical data processing paths for receiving operands at the frequency of the system clock; data output means connected to the output data latch of each of said plurality of substantially identical data processing paths for producing results at the frequency of the system clock; and each of said plurality of substantially identical data processing paths being clocked by a different path clock so as to send successive operands to different ones of said plurality of substantially identical data processing paths.