Apparatus for controlling computer pipelines for arithmetic operations on vectors

Claim 1

Apparatus for controlling first and second arithmetic pipelines in a computer, wherein said first pipeline includes first and second inputs and a first output and first arithmetic means connected between said first and second inputs and said first output, and wherein said second pipeline includes third and fourth inputs and a second output and second arithmetic means connected between said third and fourth inputs and said second output, each of said first and second arithmetic means accomplishing arithmetic operations on operands appearing at respective ones of said first, second, third and fourth inputs to derive respective resultants, said operands being arranged in a plurality of continuous streams, each stream forming a respective operand vector, said apparatus comprising: first gate means connected to said first input and having fifth, sixth and seventh inputs for selectively processing data appearing at a selected one of said fifth, sixth and seventh inputs to said first input; second gate means connected to said second input and having eighth, ninth and tenth inputs for selectively processing data appearing at a selected one of said eighth, ninth and tenth inputs to said second input; third gate means connected to said third input and having eleventh, twelfth and thirteenth inputs for selectively processing data appearing at a selected one of said eleventh, twelfth and thirteenth inputs to said third input; fourth gate means connected to said fourth input and having fourteenth, fiftennth, sixteenth and seventeenth inputs for selectively processing data appearing at a selected one of said fourteenth, fifteenth, sixteenth and seventeenth inputs to said fourth input; means connecting said fifth, eighth and seventeenth inputs to said first output to receive data from said first pipeline; means connecting said sixth and twelfth inputs to a source of one of said operand vectors; means connecting said seventh, tenth, thirteenth and sixteenth inputs to a source of data representative of a zero value; means connecting said ninth and fifteenth inputs to a source of a second of said operand vectors; means connecting said eleventh and fourteenth inputs to said second output to receive data from said second pipeline; and control means for selectively operating said first, second, third and fourth gate means to selectively process data and operands appearing at selected inputs of said first, second, third and fourth gate means to respective first, second, third and fourth inputs of said respective first and second pipelines.