Patent US5150186A successfully refreshed from Google Patents.
US5150186A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS output pull-up driver
Assignee: Micron Technology Inc
•
Filing: 1991-03-06
•
Granted: 1992-09-22
•
Expires: 2011-03-06
Abstract
Abstract A CMOS integrated circuit output terminal driver subcircuit (60) provides quick response at an output terminal (56) of an integrated circuit (50) while preventing reverse current leakage when an external high voltage, which exceeds the positive internal circuit source voltage of the integrated circuit, is imposed on the output terminal (56). The output driver subcircuit (60) additionally provides an output voltage at the output terminal that is only nominally below the internal circuit source voltage. A p-channel MOS pull-up transistor (62) is operably connected to the output terminal (56) to selectively drive it substantially to the internal circuit source voltage. A leakage prevention device (66), comprising a native n-channel transistor (68) with a low turn-on threshold voltage, is connected in series with the pull-up transistor (62) to prevent output terminal reverse current leakage back through the pull-up transistor (62) when the external high voltage is imposed upon the output terminal (56).
Inventors
- 👤 David Pinney
- 👤 Gary Johnson
- 👤 Greg Roberts
- 👤 Steve Casper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:15
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
55 words
A CMOS integrated circuit output terminal driver comprising: an output terminal; a pull-up circuit connected to the output terminal, said pull-up circuit having (a) a p-channel MOS pull-up transistor, and (b) a native n-channel MOS transistor connected in series with the p-channel pull-up transistor, wherein the native n-channel transistor has a native turn-on threshold voltage.
Claim 2
Dependent Claim
55 words
A CMOS integrated circuit output terminal driver comprising: an output terminal; a pull-up circuit connected to the output terminal, said pull-up circuit having (a) a p-channel MOS pull-up transistor, and (b) a native n-channel MOS transistor connected in series with the p-channel pull-up transistor, wherein the native n-channel transistor has a native turn-on threshold voltage.
Claim 3
Dependent Claim
25 words
The output terminal driver of claim 1, wherein the native n-channel transistor is fabricated without substantial ion implantation to maintain the native turn-on threshold voltage.
Claim 4
Dependent Claim
23 words
The output terminal driver of claim 1, wherein the native n-channel transistor is fabricated without subjecting the n-channel transistor to enhanced threshold processing.
Claim 5
Dependent Claim
21 words
The output terminal driver of claim 1, wherein the turn-on voltage of the native n-channel transistor is less than 0.5 volts.
Claim 6
Dependent Claim
21 words
The output terminal driver of claim 1, wherein the turn-on voltage of the native n-channel transistor is less than 0.2 volts.
Claim 7
Dependent Claim
27 words
The output terminal driver of claim 1, wherein the turn-on voltage of the native n-channel transistor is in the range of approximately 0.1 volts to 0.2 volts.
Claim 8
Dependent Claim
29 words
The output terminal driver of claim 1, wherein the turn-on voltage of the native n-channel transistor is lower than that of non-native n-channel transistors within the CMOS integrated circuit.
Claim 9
Dependent Claim
28 words
The output terminal driver of claim 1, further comprising a pull-down circuit having an n-channel pull-down transistor operably connected to selectively conduct between the output terminal and ground.
Claim 10
Dependent Claim
48 words
The output terminal driver of claim 1, further comprising a pull-down circuit having an n-channel pull-down transistor operably connected to selectively conduct between the output terminal and ground, wherein the turn-on threshold voltage of the native n-channel MOS transistor is lower than that of the n-channel pull-down transistor.
Claim 11
Dependent Claim
25 words
The output terminal driver of claim 1, wherein the native n-channel transistor is fabricated without increasing its turn-on threshold voltage from the original threshold voltage.
Claim 12
Dependent Claim
111 words
In a CMOS integrated circuit having an output terminal driver subcircuit for operative connection to an external circuit, the external circuit being capable of imposing an external high voltage upon the driver subcircuit, wherein the output terminal driver subcircuit comprises: an output terminal for connecting to the external circuit; a p-channel MOS pull-up transistor operably connected to the output terminal to selectively drive the output terminal substantially to an internal circuit source voltage; a native n-channel MOS transistor operably connected between the p-channel pull-up transistor and the output terminal to prevent output terminal current leakage back through the driver subcircuit when the external high voltage is imposed upon the output terminal.
Claim 13
Dependent Claim
111 words
In a CMOS integrated circuit having an output terminal driver subcircuit for operative connection to an external circuit, the external circuit being capable of imposing an external high voltage upon the driver subcircuit, wherein the output terminal driver subcircuit comprises: an output terminal for connecting to the external circuit; a p-channel MOS pull-up transistor operably connected to the output terminal to selectively drive the output terminal substantially to an internal circuit source voltage; a native n-channel MOS transistor operably connected between the p-channel pull-up transistor and the output terminal to prevent output terminal current leakage back through the driver subcircuit when the external high voltage is imposed upon the output terminal.
Claim 14
Dependent Claim
37 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor produces a voltage drop in the range of 0.1 volts to 0.2 volts between the p-channel pull-up transistor and the output terminal when conducting.
Claim 15
Dependent Claim
33 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor produces a voltage drop of less than 0.5 volts between the p-channel pull-up transistor and the output terminal when conducting.
Claim 16
Dependent Claim
33 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor produces a voltage drop of less than 0.2 volts between the p-channel pull-up transistor and the output terminal when conducting.
Claim 17
Dependent Claim
38 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor has limited ion implantation to limit the voltage drop between the p-channel pull-up transistor and the output terminal when the native n-channel transistor is conducting.
Claim 18
Dependent Claim
22 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor is fabricated without subjecting it to threshold enhancement processing.
Claim 19
Dependent Claim
26 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor is fabricated without increasing its turn-on threshold voltage from the original threshold voltage.
Claim 20
Dependent Claim
44 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor has a turn-on voltage which is less than 0.5 volts to limit the voltage drop between the p-channel pull-up transistor and the output terminal when the native n-channel transistor is conducting.
Claim 21
Dependent Claim
44 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor has a turn-on voltage which is less than 0.2 volts to limit the voltage drop between the p-channel pull-up transistor and the output terminal when the native n-channel transistor is conducting.
Claim 22
Dependent Claim
50 words
In the CMOS integrated circuit of claim 11, wherein the native n-channel transistor has a turn-on voltage which is substantially in the range of 0.1 volts to 0.2 volts to limit the voltage drop between the p-channel pull-up transistor and the output terminal when the native n-channel transistor is conducting.
Claim 23
Dependent Claim
29 words
In the CMOS integrated circuit of claim 11, further comprising an n-channel pull-down transistor operably connected to the output terminal to selectively conduct between the output terminal and ground.
Claim 24
Dependent Claim
49 words
In the CMOS integrated circuit of claim 11, further comprising an n-channel pull-down transistor operably connected to the output terminal to selectively conduct between the output terminal and ground, wherein the native turn-on threshold voltage of the n-channel MOS transistor is lower than that of the n-channel pull-down transistor.
Claim 25
Dependent Claim
68 words
A CMOS integrated circuit output terminal driver comprising: an output terminal; a pull-up circuit connected to the output terminal, said pull-up circuit having (a) a p-channel MOS pull-up transistor and (b) leakage prevention means connected in series with the p-channel pull-up transistor for preventing reverse current leakage from the output terminal back through the p-channel pull-up transistor when an external high voltage is imposed upon the output terminal.
Claim 26
Dependent Claim
68 words
A CMOS integrated circuit output terminal driver comprising: an output terminal; a pull-up circuit connected to the output terminal, said pull-up circuit having (a) a p-channel MOS pull-up transistor and (b) leakage prevention means connected in series with the p-channel pull-up transistor for preventing reverse current leakage from the output terminal back through the p-channel pull-up transistor when an external high voltage is imposed upon the output terminal.
Claim 27
Dependent Claim
18 words
The output terminal driver of claim 23, wherein the leakage prevention means comprises a native n-channel MOS transistor.
Claim 28
Dependent Claim
33 words
The output terminal driver of claim 23, wherein the leakage prevention means comprises an n-channel MOS transistor having a lower threshold voltage than standard n-channel MOS transistors within the integrated circuit output driver.
Claim 29
Dependent Claim
41 words
The output terminal driver of claim 23, further comprising an n-channel MOS pull-down transistor connected to the output terminal, wherein the leakage prevention means comprises an n-channel MOS transistor having a lower turn-on threshold voltage than the n-channel MOS pull-down transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-22 | 1996-03-23 | 1996-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-22 | 2000-03-23 | 2000-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-22 | 2004-03-23 | 2004-09-22 | $7700.00 | Window Closed / Lapsed |