Process for fabricating integrated circuits having shallow junctions

Claim 1

A process for fabricating a semiconductor device comprising the steps of treating a substrate by forming a passage through a region overlying a device junction, depositing a material over at least a portion of said region to form an electrical contact to said junction together with an electrical conducting region on the surface of said overlying region and progressing towards completing said device, characterized in that said passage has an aspect ratio of at least 1.1, said junction has a depth shallower than 2500 Å, and said electrical contact and said conductive region on said surface comprises a deposition of 1) a material that presents a barrier to the solid-state diffusion of tungsten and 2) a deposition of tungsten by interaction of said substrate with a deposition comprising WF 6 entities and a reducing agent wherein said substrate is heated to a deposition temperature in the range 250° C. to 600° C. during said tungsten deposition wherein said deposition temperature and environment is controlled such that said interaction is self-limiting with a self-limiting thickness less than said junction depth and wherein said deposition temperature is chosen such that the yield of said junctions decrease not more than 10% compared to the yield obtained for the same function having a via aspect ratio of 0.75 and having a contact of only aluminum.