US5146187A — Synthesizer loop filter for scanning receivers

Claim 1

Independent Claim 113 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter network having an input and an output, comprising: a bandwidth alterable RC filter means for restricting inputted signals to either a broad bandwidth or a narrow bandwidth coupled between the input and the output; a bandwidth reduction means for reducing the bandwidth of said RC filter to an intermediate bandwidth, said intermediate bandwidth being narrower than said broad bandwidth but broader than said narrow bandwidth, coupled between the input and the output and across said bandwidth alterable filter; and switch means for selectively coupling and decoupling said bandwidth reduction means from said input to alter the bandwidth of said alterable filter.

Claim 2

Dependent Claim 113 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter network having an input and an output, comprising: a bandwidth alterable RC filter means for restricting inputted signals to either a broad bandwidth or a narrow bandwidth coupled between the input and the output; a bandwidth reduction means for reducing the bandwidth of said RC filter to an intermediate bandwidth, said intermediate bandwidth being narrower than said broad bandwidth but broader than said narrow bandwidth, coupled between the input and the output and across said bandwidth alterable filter; and switch means for selectively coupling and decoupling said bandwidth reduction means from said input to alter the bandwidth of said alterable filter.

Claim 3

Dependent Claim 27 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter network as in claim 1, wherein said switch means is coupled directly to the input.

Claim 4

Dependent Claim 36 words

In a phase locked loop frequency synthesizer a lag filter network as in claim 1, further comprising: a first capacitor coupled between the output of said switch means and a signal ground of said RC filter.

Claim 5

Dependent Claim 24 words

In a phase locked loop frequency synthesizer, a lag filter network as in claim 1 wherein said switch means is a C-MOS transmission gate.

Claim 6

Dependent Claim 34 words

In a phase locked loop frequency synthesizer, a lag filter network as in claim 1 wherein said capacitor has an electrical capacitance of substantially greater value than of that used in said RC filter.

Claim 7

Dependent Claim 25 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit as in claim 1 wherein said switch is a C-MOS transmission gate.

Claim 8

Dependent Claim 82 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit having an input and a signal ground, comprising: a bandwidth alterable RC filter circuit capable of operating in at least three distinct bandwidth ranges coupled between the input and said signal ground; a first resistor coupled between the input and the output and across the low-pass filter; and a switch for selectively coupling and decoupling the resistor from the low-pass filter to alter the bandwidth of the lag filter.

Claim 9

Dependent Claim 82 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit having an input and a signal ground, comprising: a bandwidth alterable RC filter circuit capable of operating in at least three distinct bandwidth ranges coupled between the input and said signal ground; a first resistor coupled between the input and the output and across the low-pass filter; and a switch for selectively coupling and decoupling the resistor from the low-pass filter to alter the bandwidth of the lag filter.

Claim 10

Dependent Claim 26 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit as in claim 7, wherein said switch is coupled directly to the input.

Claim 11

Dependent Claim 33 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit as in claim 7, further comprising: a first capacitor coupled between the output of said switch and said signal ground.

Claim 12

Dependent Claim 36 words

In a phase locked loop frequency synthesizer, a bandwidth alterable lag filter circuit as in claim 7 wherein said first capacitor has an electrical capacitance of substantially greater value than that used in said low-pass filter.

Claim 13

Dependent Claim 148 words

A lag filter network for use in a loop filter in a phase locked loop frequency synthesizer comprising: input means coupled to the loop; an output means coupled to said loop; a first resistive means coupled between the input means and output means; a first switching means coupled in parallel with the first resistive means; a first capacitive means coupled between the output means and a signal ground; a second resistive means and a second capacitive means series-coupled between the output means and said signal ground; a second switching means coupled between the input means and a common node between said series-coupled second resistive and second capacitive means; a third resistive means and a third capacitive means series-coupled between the output means and said signal ground; a third switching means coupled between the input means and a common node between said series-coupled third resistive and third capacitive means.

Claim 14

Dependent Claim 148 words

A lag filter network for use in a loop filter in a phase locked loop frequency synthesizer comprising: input means coupled to the loop; an output means coupled to said loop; a first resistive means coupled between the input means and output means; a first switching means coupled in parallel with the first resistive means; a first capacitive means coupled between the output means and a signal ground; a second resistive means and a second capacitive means series-coupled between the output means and said signal ground; a second switching means coupled between the input means and a common node between said series-coupled second resistive and second capacitive means; a third resistive means and a third capacitive means series-coupled between the output means and said signal ground; a third switching means coupled between the input means and a common node between said series-coupled third resistive and third capacitive means.

Claim 15

Dependent Claim 22 words

The lag filter network as set forth in claim 11 wherein said first, second and third switching means are C-MOS transmission gates.

Claim 16

Dependent Claim 133 words

A lag filter network having an input, an output and an electrical circuit ground for use in a loop filter in a phase locked loop frequency synthesizer, comprising: a first switch coupled between the input and the output; a first resistor coupled in parallel with the first switch and between the input and the output; a first capacitor coupled between the output and the circuit ground; a second resistor and a second capacitor series-coupled between the output and the circuit ground; a second switch coupled between the input and a common node between said series-coupled second resistor and second capacitor; a third resistor and a third capacitor series-coupled between the output and the circuit ground; a third switch coupled between the input and common node between said series-coupled third resistor and third capacitor.

Claim 17

Dependent Claim 133 words

A lag filter network having an input, an output and an electrical circuit ground for use in a loop filter in a phase locked loop frequency synthesizer, comprising: a first switch coupled between the input and the output; a first resistor coupled in parallel with the first switch and between the input and the output; a first capacitor coupled between the output and the circuit ground; a second resistor and a second capacitor series-coupled between the output and the circuit ground; a second switch coupled between the input and a common node between said series-coupled second resistor and second capacitor; a third resistor and a third capacitor series-coupled between the output and the circuit ground; a third switch coupled between the input and common node between said series-coupled third resistor and third capacitor.

Claim 18

Dependent Claim 21 words

The lag filter network as set forth in claim 13 wherein said first, second and third switches are C-MOS transmission gates.

Claim 19

Independent Claim 96 words

A method of providing at least one intermediate frequency bandwidth mode of operation in a phase lock loop frequency synthesizer, said phase locked loop including a voltage controlled oscillator coupled to the output of a loop filter, the loop filter comprising a bandwidth alterable lag filter having at least one bandwidth altering resistor, and a voltage transient suppression capacitor, connected to said resistor comprising the step of: switching from a wide bandwidth mode of operation to an intermediate frequency bandwidth mode of operation by electrically coupling said resistor and said capacitor into the lag filter network.

Claim 20

Independent Claim 96 words

A method of providing at least one intermediate frequency bandwidth mode of operation in a phase lock loop frequency synthesizer, said phase locked loop including a voltage controlled oscillator coupled to the output of a loop filter, the loop filter comprising a bandwidth alterable lag filter having at least one bandwidth altering resistor, and a voltage transient suppression capacitor, connected to said resistor comprising the step of: switching from a wide bandwidth mode of operation to an intermediate frequency bandwidth mode of operation by electrically coupling said resistor and said capacitor into the lag filter network.

Claim 21

Dependent Claim 58 words

A method of providing at least one intermediate bandwidth mode of operation in a phase lock loop frequency synthesizer as described in claim 15 further comprising the step of: simultaneously decoupling said resistor and said voltage transient suppression capacitor from an input of said lag filter when switching from an intermediate frequency bandwidth to a narrower frequency bandwidth.

Claim 22

Independent Claim 235 words

A method of providing a wide bandwidth mode of operation, a narrow bandwidth mode of operation and at least one intermediate frequency bandwidth mode of operation in an adaptive phase lock loop frequency synthesizer without creating substantial switching transients which disturb the output signal, the phase locked loop including a voltage controlled oscillator coupled to the output of a loop filter, said loop filter comprising a bandwidth alterable lag filter network having a low-pass filter network comprising at least one first controllable switch and at least one bandwidth altering resistor, an additional second controllable switch coupled to an input of said loop filter and in series with said bandwidth altering resistor, and a voltage transient suppression capacitor coupled between an output of said second controllable switch and a circuit ground of said lag filter, comprising the steps of: electrically bypassing the low-pass filter by setting the state of said at least one first controllable switch in the low-pass filter network to provide a wide bandwidth mode of operation; changing the state of said at least one first controllable switch to effectively couple said low-pass filter including said extraneous resistor and capacitor into the lag filter network to provide an intermediate frequency bandwidth mode of operation; and subsequently changing the state of the second controllable switch to electrically rearrange said bandwidth altering resistor within the low pass filter to provide a narrow bandwidth mode of operation.

Claim 23

Independent Claim 235 words

A method of providing a wide bandwidth mode of operation, a narrow bandwidth mode of operation and at least one intermediate frequency bandwidth mode of operation in an adaptive phase lock loop frequency synthesizer without creating substantial switching transients which disturb the output signal, the phase locked loop including a voltage controlled oscillator coupled to the output of a loop filter, said loop filter comprising a bandwidth alterable lag filter network having a low-pass filter network comprising at least one first controllable switch and at least one bandwidth altering resistor, an additional second controllable switch coupled to an input of said loop filter and in series with said bandwidth altering resistor, and a voltage transient suppression capacitor coupled between an output of said second controllable switch and a circuit ground of said lag filter, comprising the steps of: electrically bypassing the low-pass filter by setting the state of said at least one first controllable switch in the low-pass filter network to provide a wide bandwidth mode of operation; changing the state of said at least one first controllable switch to effectively couple said low-pass filter including said extraneous resistor and capacitor into the lag filter network to provide an intermediate frequency bandwidth mode of operation; and subsequently changing the state of the second controllable switch to electrically rearrange said bandwidth altering resistor within the low pass filter to provide a narrow bandwidth mode of operation.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-09-08	1996-03-09	1996-09-08	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-09-08	2000-03-09	2000-09-08	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-09-08	2004-03-09	2004-09-08	$7700.00	Window Closed / Lapsed

Synthesizer loop filter for scanning receivers

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