Fast acquisition phase-lock loop

Claim 2

In a phase-locked loop circuit receiving input signals and having means for generating reference signals, loop filter means for controlling said reference signal generating means, and an input stage to drive said loop filter means as a function of said input signals and said reference signals, the improvement being in said input stage and comprising: up/down counter means for receiving said input signals and said reference signals and producing output signals, representative of the magnitude and polarity of the difference between the frequency of said input signals and the frequency of said reference signals, over an extended range greater than one-half of the frequency of said input signals, said up/down counter means including at least one internal buffer state for use in determining the phase difference between said input signals and said reference signals.

Claim 3

The phase-locked loop circuit of claim 1, wherein the output signal of said input stage is a signal whose magnitude is substantially linearly porportional to said magnitude of the difference between said frequencies.

Claim 4

In a phase-locked loop circuit receiving circuit input data signals and having means for generating reference signals, loop filter means for controlling said means for generating reference signals, and an input stage for driving said loop filter means, the improvement being in said input stage and comprising: means for receiving as input signals said circuit input data signals and said reference signals and generating output signals along first and second signal paths according to the polarity of the difference in frequency between said circuit input data signals and said reference signals, said output signals along each of said first and second signal paths being proportional to the magnitude of said difference in frequency; and means for receiving said circuit input data signals, said reference signals, and said output signals from along said first and second signal paths, associating said circuit input data signals with said output signals from along said first signal path and said reference signals with said output signals from along said second signal path, and producing control signals to drive said loop filter means when both signals of either pair of said associated signals are present simultaneously, said control signals being proportional to said difference in frequency up to a predetermined level.

Claim 5

In a phase-locked loop circuit receiving circuit input data signals and having means for generating reference signals, loop filter means for controlling said means for generating reference signals, and an input stage for driving said loop filter means, the improvement being in said input stage and comprising: means for receiving as input signals said circuit input data signals and said reference signals and generating output signals along first and second signal paths according to the polarity of the difference in frequency between said circuit input data signals and said reference signals, said output signals along each of said first and second signal paths being proportional to the magnitude of said difference in frequency; and means for receiving said circuit input data signals, said reference signals, and said output signals from along said first and second signal paths, associating said circuit input data signals with said output signals from along said first signal path and said reference signals with said output signals from along said second signal path, and producing control signals to drive said loop filter means when both signals of either pair of said associated signals are present simultaneously, said control signals being proportional to said difference in frequency up to a predetermined level.

Claim 6

The phase-locked loop circuit of claim 3, wherein said means for generating output signals along first and second signal paths includes up/down counter means for producing top and bottom signals along said first and second signal paths, respectively, as a function of the positive and negative polarity, respectively, of said difference in frequency and at a rate proportional to the magnitude of said difference in frequency such that said top signals are associated with said circuit input data signals and said bottom signals are associated with said reference signals.

Claim 7

The phase-locked loop circuit of claim 4, wherein said up/down counter means prevents generation of said control signals when said difference in frequency is substantially zero.

Claim 8

The phase-locked loop circuit of claim 4, wherein said means for associating said circuit input data signals and said top signals and said means for associating said reference signals and said bottom signals each includes monostable multivibrator means triggered by one of said pair of associated signals and enabled by the other of said pair of associated signals.

Claim 9

The phase-locked loop circuit of claim 4, wherein said control signals include overflow and underflow signals each responsive to one of said pair of associated signals, and said up/down counter means further produces second top and second bottom signals as a function of the difference in phase between said circuit input data signals and said reference signals, and including means for applying said second top and second bottom signals as second control signals to drive said loop filter means.

Claim 10

The phase-locked loop circuit of claim 7, wherein said up/down counter means includes means for preventing generation of either of said overflow or underflow signals, but not said second top or second bottom signals, when said difference in frequency is substantially zero.

Claim 11

A proportional frequency detector, for use in phase-locked loop circuits having means for generating reference signals, loop filter means for controlling said means for generating reference signals, and input stage means for driving said loop filter means, comprising: means for receiving input data signals and said reference signals, comparing the frequencies of these two signals, and producing output signals representative of the magnitude and polarity of the difference between said frequencies of these two signals; and means for receiving said output signals and producing, as a function of said input data signals and said reference signals, control signals for driving said loop filter means, said control signals being proportional to the magnitude of the difference between said frequencies of these two signals up to a predetermined level and being fixed maximum values when said predetermined level is exceeded.

Claim 12

A proportional frequency detector, for use in phase-locked loop circuits having means for generating reference signals, loop filter means for controlling said means for generating reference signals, and input stage means for driving said loop filter means, comprising: means for receiving input data signals and said reference signals, comparing the frequencies of these two signals, and producing output signals representative of the magnitude and polarity of the difference between said frequencies of these two signals; and means for receiving said output signals and producing, as a function of said input data signals and said reference signals, control signals for driving said loop filter means, said control signals being proportional to the magnitude of the difference between said frequencies of these two signals up to a predetermined level and being fixed maximum values when said predetermined level is exceeded.

Claim 13

The proportional frequency detector of claim 9, wherein means are provided for preventing the generation of said control signals when the magnitude of said difference between said frequencies is substantially zero.

Claim 14

A proportional frequency detector, for use in phase-locked loop circuits, comprising: up/down counter means for receiving input data signals and reference signals and producing top and bottom output signals representing the polarity and magnitude of the frequency difference between these two received signals; overflow means for receiving said input data signals and said top output signals and producing overflow output signals when the frequency of said input data signals exceeds the frequency of said reference signals; underflow means for receiving said reference signals and said bottom output signals and producing underflow output signals when the frequency of said reference signals exceeds the frequency of said input data signals; and means for summing said overflow output signals and said underflow output signals and producing a combined output signal proportional to the polarity and magnitude of said frequency difference up to a predetermined saturation level.

Claim 15

A proportional frequency detector, for use in phase-locked loop circuits, comprising: up/down counter means for receiving input data signals and reference signals and producing top and bottom output signals representing the polarity and magnitude of the frequency difference between these two received signals; overflow means for receiving said input data signals and said top output signals and producing overflow output signals when the frequency of said input data signals exceeds the frequency of said reference signals; underflow means for receiving said reference signals and said bottom output signals and producing underflow output signals when the frequency of said reference signals exceeds the frequency of said input data signals; and means for summing said overflow output signals and said underflow output signals and producing a combined output signal proportional to the polarity and magnitude of said frequency difference up to a predetermined saturation level.

Claim 16

The proportional frequency detector of claim 11, wherein said overflow and underflow means produce output signals of predeterminable, fixed pulse widths, and said predetermined saturation level is a function of those pulse widths.