← Back to Patent Explorer
US4510461A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase lock loop having switchable filters and oscillators

Assignee: St Clair Intellectual Property Consultants Inc
•
Filing: 1982-07-22
•
Granted: 1985-04-09
•
Expires: 2002-07-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A phase lock circuit including a phase/frequency detector, a plurality of selectable filters, and a plurality of variable frequency signal generators connected in a loop to lock an output signal to an input signal. An out-of-frequency-range condition detector is provided to facilitate automatic selection of an appropriate in-range combination of filter and signal generator to cause lock to occur.

Inventors

  • 👤 Eric J. Dickes
  • 👤 Thomas C. Hill, III
  • 👤 Robert T. Flegal

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 00:30
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/10; H03L7/107; H03L7/1075; Y; Y10; Y10S; Y10S331/00; Y10S331/02

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 105 words
A phase lock circuit, comprising: means for detecting phase and frequency differences between an input signal and an output signal and generating a detection signal representative of said differences; filter means responsive to said detection signal for producing a control voltage, said filter means having a plurality of selectable frequency ranges; variable-frequency signal generation means responsive to said control voltage for producing said output signal, said variable-frequency signal generation means having a plurality of selectable frequency ranges matchable with those of said filter means; and selection means responsive to said control voltage for selecting filter means and variable-frequency signal generation means having matched frequency ranges.
Claim 2
Dependent Claim 105 words
A phase lock circuit, comprising: means for detecting phase and frequency differences between an input signal and an output signal and generating a detection signal representative of said differences; filter means responsive to said detection signal for producing a control voltage, said filter means having a plurality of selectable frequency ranges; variable-frequency signal generation means responsive to said control voltage for producing said output signal, said variable-frequency signal generation means having a plurality of selectable frequency ranges matchable with those of said filter means; and selection means responsive to said control voltage for selecting filter means and variable-frequency signal generation means having matched frequency ranges.
Claim 3
Dependent Claim 41 words
A phase lock circuit in accordance with claim 1 wherein said phase difference detecting means comprises logic circuit means for generating electrical pulses the width of which is proportional to the phase difference between said input signal and said output signal.
Claim 4
Dependent Claim 28 words
A phase lock circuit in accordance with claim 1 wherein said variable frequency signal generation means comprises a plurality of voltage-controlled oscillators each having a different frequency range.
Claim 5
Dependent Claim 65 words
A phase lock circuit in accordance with claim 1 wherein said selection means comprises means for receiving said control voltage and detecting therefrom an out-of-range condition, and means responsive to said out-of-range condition for selecting a combination of said filter means and said variable frequency signal generation means which will cause said output signal to lock to the frequency and phase of said input signal.
Claim 6
Dependent Claim 62 words
A phase lock circuit in accordance with claim 4 wherein said out-of-range condition detecting means comprises means for comparing said control voltage with first and second reference voltage levels, wherein a control voltage value in excess of said first reference voltage level indicates an over-range condition, and a control voltage value less than said second reference voltage level indicates an under-range condition.

References Cited (Backward Citations)

US3431509A Cited
US3538450A Cited
US3729688A Cited
US3909735A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-04-08 1988-10-08 1989-04-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-04-08 1992-10-08 1993-04-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-04-08 1996-10-08 1997-04-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag