US4752749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast response tuner
Assignee: Boeing North American Inc
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Filing: 1986-12-22
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Granted: 1988-06-21
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Expires: 2006-12-22
Abstract
Abstract Frequency disturbances caused by voltage fluctuations which occur when a bandwidth limiting lag network is switched in and out of a frequency synthesizer circuit to provide the wide bandwidth necessary for fast frequency hopping are eliminated by the invention. Rather than switching a parallel charging source for the large network capacitor out of the circuit during each hopping interval, the capacitor is charged in series to a constant level during narrow bandwidth mode and charged on both plates in consonance with the input voltage during the wide bandwidth mode to thereby render the lag network active during the narrowband mode and transparent during the wideband mode.
Inventors
- 👤 George A. Moger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:22
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/08; H03L7/085; H03L7/093; H03L7/10; H03L7/107; H03L7/1075
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
76 words
In a phase locked loop circuit producing an alternating current output signal of a predetermined frequency, circuitry for altering the bandwidth of the loop without disturbing the frequency of the output signal, comprising: a capacitor bearing an electrical quantity determinative of an aspect of the bandwidth; means for coupling a low impedance alternating current sink to the capacitor; and means for selectively switching the low impedance providing means into and out of circuit with said capacitor.
Claim 2
Dependent Claim
76 words
In a phase locked loop circuit producing an alternating current output signal of a predetermined frequency, circuitry for altering the bandwidth of the loop without disturbing the frequency of the output signal, comprising: a capacitor bearing an electrical quantity determinative of an aspect of the bandwidth; means for coupling a low impedance alternating current sink to the capacitor; and means for selectively switching the low impedance providing means into and out of circuit with said capacitor.
Claim 3
Dependent Claim
67 words
In a phase locked loop circuit as described in claim 1 wherein said means for providing a low impedance alternating current sink comprises: means for providing loop signals to the first plate of said capacitor; means for providing said loop signals to the second plate of said capacitor; and means for selectively coupling and decoupling said loop signals to and from said second plate of said capacitor.
Claim 4
Dependent Claim
51 words
In a phase locked loop circuit producing an alternating current output signal of a predetermined frequency, circuitry as described in claim 2 further including means for maintaining a direct current voltage on said second plate of said capacitor while said loop signals are decoupled from said second plate of said capacitor.
Claim 5
Dependent Claim
80 words
In a phase locked loop circuit producing an alternating current output signal of a predetermined frequency, circuitry as described in claim 3 wherein said means for providing loop signals to said first plate of said capacitor comprises: a first resistor coupled to the source of said loop signals; and a second resistor coupled to said first resistor and to said first plate of said capacitor, said node between the first and second resistors defining an output terminal from the circuitry.
Claim 6
Dependent Claim
55 words
In a phase locked loop circuit producing an alternating current output signal of a predetermined frequency, circuitry as described in claim 3 wherein said means for providing loop signals to said second plate of said capacitor comprises: an amplifier coupled to said second plate; and a resistor-capacitor network coupled to the input of the amplifier.
Claim 7
Dependent Claim
96 words
Circuitry for selectively altering the bandwidth of a phase locked loop frequency synthesizer without disturbing the frequency thereof, comprising: input means coupled to signals in the loop; a capacitor for determining an aspect of the bandwidth of said loop; means coupled to the input means, for providing said loop signals to a first plate of the capacitor; means coupled to the input means for providing said loop signals to a second plate of said capacitor; and means for selectively coupling and decoupling said loop signals providing means to and from said second plate of said capacitor.
Claim 8
Dependent Claim
96 words
Circuitry for selectively altering the bandwidth of a phase locked loop frequency synthesizer without disturbing the frequency thereof, comprising: input means coupled to signals in the loop; a capacitor for determining an aspect of the bandwidth of said loop; means coupled to the input means, for providing said loop signals to a first plate of the capacitor; means coupled to the input means for providing said loop signals to a second plate of said capacitor; and means for selectively coupling and decoupling said loop signals providing means to and from said second plate of said capacitor.
Claim 9
Dependent Claim
34 words
Circuitry as described in claim 6 further including means for maintaining a DC voltage on said second plate of said capacitor while said loop signals are decoupled from said second plate of said capacitor.
Claim 10
Dependent Claim
30 words
Circuitry as described in claim 7 wherein said maintaining means comprises: an amplifier coupled to said second capacitor plate; and a resistor-capacitor network coupled to the input of the amplifier.
Claim 11
Dependent Claim
14 words
Circuitry as described in claim 8 wherein said selective coupling means comprises a switch.
Claim 12
Dependent Claim
67 words
In a phase locked loop frequency synthesizer, a lag network having an input and an output, comprising: a first resistor coupled between the input and the output; a second resistor coupled to the first resistor and said output; a capacitor coupled to the second resistor; means for coupling a low impedance load to said capacitor; and means for selectively decoupling the low impedance load from said capacitor.
Claim 13
Dependent Claim
67 words
In a phase locked loop frequency synthesizer, a lag network having an input and an output, comprising: a first resistor coupled between the input and the output; a second resistor coupled to the first resistor and said output; a capacitor coupled to the second resistor; means for coupling a low impedance load to said capacitor; and means for selectively decoupling the low impedance load from said capacitor.
Claim 14
Dependent Claim
91 words
In a phase locked loop frequency synthesizer, a lag network as described in claim 10 wherein said low impedance providing means comprises: a first amplifier the output of which is coupled to said capacitor; a capacitor coupled to the input of the first amplifier; a resistor coupled to the capacitor and the input of said amplifier on one end and to said selective coupling means on the other end; and a second amplifier having its output coupled to the resistor and said selective coupling means and its input to said input.
Claim 15
Dependent Claim
29 words
In a phase locked loop frequency synthesizer, a lag network as described in claim 11 wherein said selective coupling means is a switch coupled in parallel to said resistor.
Claim 16
Dependent Claim
148 words
A lag network for use in a phase locked loop frequency synthesizer comprising: input means coupled to the loop; output means coupled to said loop; a first resistor coupled between the input means and the output means; a second resistor coupled to said input means and the first resistor; a first capacitor coupled to the second resistor; a first amplifier having its output coupled to the first capacitor; a second capacitor coupled to the input of said first amplifier; a third resistor having a first lead coupled to the input of said first amplifier and to the second capacitor; switch means having a first lead coupled to said first amplifier in parallel with the third resistor; and a second amplifier having its output coupled to a second lead of said third resistor and a second lead of the switch means and its input coupled to said input means.
Claim 17
Dependent Claim
148 words
A lag network for use in a phase locked loop frequency synthesizer comprising: input means coupled to the loop; output means coupled to said loop; a first resistor coupled between the input means and the output means; a second resistor coupled to said input means and the first resistor; a first capacitor coupled to the second resistor; a first amplifier having its output coupled to the first capacitor; a second capacitor coupled to the input of said first amplifier; a third resistor having a first lead coupled to the input of said first amplifier and to the second capacitor; switch means having a first lead coupled to said first amplifier in parallel with the third resistor; and a second amplifier having its output coupled to a second lead of said third resistor and a second lead of the switch means and its input coupled to said input means.
Claim 18
Dependent Claim
20 words
A lag filter network as described in claim 13 wherein said first and second amplifiers are configured for unity gain.
Claim 19
Dependent Claim
15 words
A lag filter network as described in claim 13 wherein said amplifiers are operational amplifiers.
Claim 20
Dependent Claim
97 words
In a phase-locked-loop having a phase comparator, a loop filter and a voltage-controlled-oscillator, a switchable lag network comprising: a first resistor coupled between the loop filter and the voltage controlled oscillator; a second resistor coupled both to the first resistor and the voltage controlled oscillator; a capacitor having a first side coupled to the second resistor; means coupled to a second side of the capacitor for providing a voltage related to the voltage at the output of the loop filter; and means for selectively switching said providing means into and out of electrical engagement with said capacitor.
Claim 21
Dependent Claim
97 words
In a phase-locked-loop having a phase comparator, a loop filter and a voltage-controlled-oscillator, a switchable lag network comprising: a first resistor coupled between the loop filter and the voltage controlled oscillator; a second resistor coupled both to the first resistor and the voltage controlled oscillator; a capacitor having a first side coupled to the second resistor; means coupled to a second side of the capacitor for providing a voltage related to the voltage at the output of the loop filter; and means for selectively switching said providing means into and out of electrical engagement with said capacitor.
Claim 22
Independent Claim
95 words
A method of altering the bandwidth of a phase locked loop frequency synthesizer without disturbing the frequency of the output signal, said phase locked loop containing a voltage controlled oscillator fed through a lag network having a capacitor, comprising the steps of: providing loop signals to a first plate of the capacitor; providing a direct current signal to a second plate of said capacitor; providing loop signals to the second plate of said capacitor to provide a wideband state; and selectively ceasing providing loop signals to said second capacitor plate to provide a narrowband state.
Claim 23
Independent Claim
95 words
A method of altering the bandwidth of a phase locked loop frequency synthesizer without disturbing the frequency of the output signal, said phase locked loop containing a voltage controlled oscillator fed through a lag network having a capacitor, comprising the steps of: providing loop signals to a first plate of the capacitor; providing a direct current signal to a second plate of said capacitor; providing loop signals to the second plate of said capacitor to provide a wideband state; and selectively ceasing providing loop signals to said second capacitor plate to provide a narrowband state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-21 | 1991-12-21 | 1992-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-21 | 1995-12-21 | 1996-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-21 | 1999-12-21 | 2000-06-21 | $7700.00 | Window Closed / Lapsed |