Phase-locked loop circuit with variable bandwidth filter

Claim 2

A phase-locked loop circuit comprising: oscillator means for producing an oscillation signal; phase comparator means for phase-comparing an input signal with said oscillation signal to produce a phase-compared signal; detecting means for detecting when said phase-locked loop circuit is locked within a predetermined frequency range and for producing a lock detecting signal corresponding to said detection in response to said input signal and said oscillation signal; and filter means for producing an output signal in response to said phase-compared signal and said lock detecting signal to lock the frequency of said oscillation signal to the frequency of said input signal, said filter means including variable current source means for producing a variable current having a first value in the presence of and a second value in the absence of said lock detecting signal, a filter circuit supplying said output signal, and control means connected to said filter circuit for producing said output signal in response to said variable current and said phase-compared signal, said control means including a differential amplifier comprised of first and second transistors, each having a base, collector and emitter terminal, said filter circuit being connected to the collector terminal of one of said transistors, said variable current being supplied to the emitter terminals of said transistors, and said phase-compared signal being supplied to the base terminals of said transistors.

Claim 3

A phase-locked loop circuit according to claim 1; in which said filter circuit includes a resistive element and a capacitive element connected in series between the collector terminal of said one of said transistors and a reference potential.

Claim 4

A phase-locked loop circuit according to claim 1; in which said control means includes current mirror means connected to the collector terminals of said first and second transistors.

Claim 5

A phase-locked loop circuit according to claim 1; in which the emitter terminals of said first and second transistors are multi-emitter terminals.

Claim 6

A phase-locked loop circuit according to claim 4; in which said variable current source means includes a first constant current source which supplies a constant current to said control means and a second current source which supplies a second current to said control means only when the phase-locked loop circuit is not locked within said predetermined frequency range; and said multi-emitter terminals include first emitter terminals having first areas and connected to said first constant current source and second emitter terminals having second, larger areas and connected to said second current source.

Claim 7

A phase-locked loop circuit according to claim 1; in which said control means includes non-linear means connected between the emitter terminals of said transistors and said variable current source means.

Claim 8

A phase-locked loop circuit according to claim 6; in which said control means includes resistive means connected in parallel with said non-linear means.

Claim 9

A phase-locked loop circuit comprising: oscillator means for producing an oscillation signal; phase comparator means for phase-comparing an input signal with said oscillation signal to produce a phase-compared signal; detecting means for detecting when said phase-locked loop circuit is locked within a predetermined frequency range and for producing a lock detecting signal corresponding to said detection in response to said input signal and said oscillation signal; and filter means for producing an output signal in response to said phase-compared signal and said lock detecting signal to lock the frequency of said oscillation signal to the frequency of said input signal, said filter means including variable current source means for producing a variable current having a first value in the presence of and a second value in the absence of said lock detecting signal, a filter circuit supplying said output signal, and control means connected to said filter circuit for producing said output signal in response to said variable current and said phase-compared signal, said control means including a first transistor pair comprising first and second transistors and a second transistor pair comprising third and fourth transistors, each of said transistors having a base, emitter and collector terminal, the base terminals of said first and second transistors being connected in common, the base terminals of said third and fourth transistors being connected in common, the collector terminals of said first and second transistors being connected in common, the collector terminals of said third and fourth transistors being connected in common, and the emitter terminals of said first through fourth transistors being connected to said variable current source means.

Claim 10

A phase-locked loop circuit comprising: oscillator means for producing an oscillation signal; phase comparator means for phase-comparing an input signal with said oscillation signal to produce a phase-compared signal; detecting means for detecting when said phase-locked loop circuit is locked within a predetermined frequency range and for producing a lock detecting signal corresponding to said detection in response to said input signal and said oscillation signal; and filter means for producing an output signal in response to said phase-compared signal and said lock detecting signal to lock the frequency of said oscillation signal to the frequency of said input signal, said filter means including variable current source means for producing a variable current having a first value in the presence of and a second value in the absence of said lock detecting signal, a filter circuit supplying said output signal, and control means connected to said filter circuit for producing said output signal in response to said variable current and said phase-compared signal, said control means including a first transistor pair comprising first and second transistors and a second transistor pair comprising third and fourth transistors, each of said transistors having a base, emitter and collector terminal, the base terminals of said first and second transistors being connected in common, the base terminals of said third and fourth transistors being connected in common, the collector terminals of said first and second transistors being connected in common, the collector terminals of said third and fourth transistors being connected in common, and the emitter terminals of said first through fourth transistors being connected to said variable current source means.

Claim 11

A phase-locked loop circuit according to claim 8; in which said variable current source means includes a first constant current source and a second current source; and the emitter terminals of said first and third transistors are connected to said first constant current source and the emitter terminals of said second and fourth transistors are connected to said second current source.

Claim 12

A phase-locked loop circuit according to claim 9; in which said control means includes resistive means connected between the emitter terminals of said first and third transistors and said first constant current source.